131 lines
4.0 KiB
C
131 lines
4.0 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*******************************************************************
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* Copyright (C) 2004 Intel Corporation
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*
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* DESCRIPTION:
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*
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* AUTHOR:
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*
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* HISTORY:
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*
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*******************************************************************/
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#ifndef __ARM946E_S_H__
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#define __ARM946E_S_H__
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//define ARM946e working modes
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#define ARM946E_USR_MODE (0x10)
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#define ARM946E_FIQ_MODE (0x11)
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#define ARM946E_IRQ_MODE (0x12)
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#define ARM946E_SVC_MODE (0x13)
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#define ARM946E_ABT_MODE (0x17)
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#define ARM946E_UND_MODE (0x1B)
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#define ARM946E_SYS_MODE (0x1F)
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#define ARM946E_IRQ_BIT (0x80) // when I bit is set, IRQ is disabled
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#define ARM946E_FIQ_BIT (0x40) // when F bit is set, FIQ is disabled
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#define ARM946E_MODE_MASK (0x1F)
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// User & System mode registers
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#define ARM9_CORE_R0 (0x0)
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#define ARM9_CORE_R1 (0x1)
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#define ARM9_CORE_R2 (0x2)
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#define ARM9_CORE_R3 (0x3)
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#define ARM9_CORE_R4 (0x4)
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#define ARM9_CORE_R5 (0x5)
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#define ARM9_CORE_R6 (0x6)
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#define ARM9_CORE_R7 (0x7)
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#define ARM9_CORE_R8 (0x8)
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#define ARM9_CORE_R9 (0x9)
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#define ARM9_CORE_R10 (0xA)
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#define ARM9_CORE_R11 (0xB)
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#define ARM9_CORE_R12 (0xC)
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#define ARM9_CORE_R13 (0xD)
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#define ARM9_CORE_SP (0xD)
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#define ARM9_CORE_R14 (0xE)
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#define ARM9_CORE_LR (0xE)
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#define ARM9_CORE_R15 (0xF)
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#define ARM9_CORE_PC (0xF)
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#define ARM9_CORE_CPSR (0x10)
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#define ARM9_CORE_A1 (0x0)
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#define ARM9_CORE_A2 (0x1)
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#define ARM9_CORE_A3 (0x2)
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#define ARM9_CORE_A4 (0x3)
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#define ARM9_CORE_V1 (0x4)
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#define ARM9_CORE_V2 (0x5)
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#define ARM9_CORE_V3 (0x6)
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#define ARM9_CORE_V4 (0x7)
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#define ARM9_CORE_V5 (0x8)
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#define ARM9_CORE_V6 (0x9)
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#define ARM9_CORE_V7 (0xA)
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#define ARM9_CORE_V8 (0xB)
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#define ARM9_CORE_SB (0x9)
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#define ARM9_CORE_SL (0xA)
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#define ARM9_CORE_FP (0xB)
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#define ARM9_CORE_IP (0xC)
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// Supervisor mode additional registers
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#define ARM9_CORE_R13_SVC (0x1000000D)
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#define ARM9_CORE_SP_SVC (0x1000000D)
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#define ARM9_CORE_R14_SVC (0x1000000E)
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#define ARM9_CORE_LR_SVC (0x1000000E)
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#define ARM9_CORE_SPSR_SVC (0x10000010)
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// Abort mode additional registers
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#define ARM9_CORE_R13_ABT (0x2000000D)
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#define ARM9_CORE_SP_ABT (0x2000000D)
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#define ARM9_CORE_R14_ABT (0x2000000E)
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#define ARM9_CORE_LR_ABT (0x2000000E)
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#define ARM9_CORE_SPSR_ABT (0x20000010)
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// Undefined mode additional registers
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#define ARM9_CORE_R13_UND (0x3000000D)
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#define ARM9_CORE_SP_UND (0x3000000D)
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#define ARM9_CORE_R14_UND (0x3000000E)
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#define ARM9_CORE_LR_UND (0x3000000E)
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#define ARM9_CORE_SPSR_UND (0x30000010)
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// Interrupt mode additional registers
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#define ARM9_CORE_R13_IRQ (0x4000000D)
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#define ARM9_CORE_SP_IRQ (0x4000000D)
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#define ARM9_CORE_R14_IRQ (0x4000000E)
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#define ARM9_CORE_LR_IRQ (0x4000000E)
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#define ARM9_CORE_SPSR_IRQ (0x40000010)
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// Fast Interrupt mode additional registers
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#define ARM9_CORE_R8_FIQ (0x50000008)
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#define ARM9_CORE_R9_FIQ (0x50000009)
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#define ARM9_CORE_R10_FIQ (0x5000000A)
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#define ARM9_CORE_R11_FIQ (0x5000000B)
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#define ARM9_CORE_R12_FIQ (0x5000000C)
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#define ARM9_CORE_R13_FIQ (0x5000000D)
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#define ARM9_CORE_SP_FIQ (0x5000000D)
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#define ARM9_CORE_R14_FIQ (0x5000000E)
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#define ARM9_CORE_LR_FIQ (0x5000000E)
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#define ARM9_CORE_SPSR_FIQ (0x50000010)
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// Function prototypes
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void Arm946eRestoreInterrupts(UINT32 ir);
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UINT32 Arm946eDisableInterrupts(void);
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UINT32 Arm946eEnableInterrupts(void);
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/* External parameters used for memory initialization */
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extern void asm_Arm9SetZeroInitialized(void);
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/** external data **/
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extern UINT32 TCT_System_Limit;
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extern void asm_Arm946e_flush_caches(void);
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#endif //__ARM946E_S_H__
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