370 lines
13 KiB
C
370 lines
13 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*******************************************************************
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* Copyright (C) 2004 Intel Corporation
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*
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* DESCRIPTION:
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*
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* AUTHOR:
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*
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* Date Created:3/21/2004 8:32:31 AM
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*
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* HISTORY:
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* SE 05 December 2007 TTC modfications
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* YK 21 March 2007 duplicated APIs to reside on both DDR (for init) and TCM (for D2 exit)
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*
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* NOTE:
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* APIs with _DS _TCS mean they are duplicated twice, to run at init from DDR
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* and to run from TCM on D2 exit. The source files are duplicated in CC and controlled
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* by compilation switch and MACROS of FUNCNAME_CTRL, TABLENAME_CTRL
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*
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*******************************************************************/
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#if !defined (ARM946E_SCP15_H)
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#define ARM946E_SCP15_H
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/** include files **/
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#include "arm946e_config.h"
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#include "global_types.h"
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#if defined (TTC_CORE_ARM946_CP15)
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#include "sCP15_l2cache.h"
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#endif
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#include "arm946e_smpu.h"
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#if defined (TTC_CORE_ARM946_CP15)
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/* TTC - maintaining legacy API for core package routines */
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#define Arm946eCP15GetControlReg_TCS Arm946eCP15GetControlReg_DS
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#define Arm946eCP15GetMPUEnalbe_TCS Arm946eCP15GetMPUEnalbe_DS
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#define Arm946eCP15SetInstTCMEnable_TCS Arm946eCP15SetInstTCMEnable_DS
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#define Arm946eCP15SetDataTCMEnable_TCS Arm946eCP15SetDataTCMEnable_DS
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#define Arm946eCP15SetInstCacheEnable_TCS Arm946eCP15SetInstCacheEnable_DS
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#define Arm946eCP15SetDataCacheEnable_TCS Arm946eCP15SetDataCacheEnable_DS
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#define Arm946eCP15SetMPUEnalbe_TCS Arm946eCP15SetMPUEnalbe_DS
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#define Arm946eCP15SetMPUDisable_TCS Arm946eCP15SetMPUDisable_DS
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#define Arm946eCP15RestoreMPUEnableDisable_TCS Arm946eCP15RestoreMPUEnableDisable_DS
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#define Arm946eCP15SetRegionAccessPermission_TCS Arm946eCP15SetRegionAccessPermission_DS
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#define Arm946eCP15SetRegionBaseAndSizeReg_TCS Arm946eCP15SetRegionBaseAndSizeReg_DS
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#define Arm946eCP15SetDataTCMRegionBaseAndSizeReg_TCS Arm946eCP15SetDataTCMRegionBaseAndSizeReg_DS
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#define Arm946eCP15SetInstTCMRegionBaseAndSizeReg_TCS Arm946eCP15SetInstTCMRegionBaseAndSizeReg_DS
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#define asm_Arm9ReadCP15_TCS asm_Arm9ReadCP15_DS
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#define asm_Arm9WriteCP15_TCS asm_Arm9WriteCP15_DS
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#endif
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typedef union
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{
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struct
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{
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UINT32 pmuEnable:1;
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UINT32 :1 ; // reserved
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UINT32 dCacheEnable:1 ;
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UINT32 :4 ; // reserved
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UINT32 bigEndian:1;
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#if defined (TTC_CORE_ARM946_CP15)
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UINT32 :3 ; // reserved
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UINT32 bpuEnable:1;
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#else
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UINT32 :4 ; // reserved
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#endif
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UINT32 iCacheEnable:1;
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UINT32 alternateVectorSelect:1;
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UINT32 roundRobinReplacement:1;
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UINT32 diableLoadingTIBT:1;
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UINT32 dTCMEnable:1;
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UINT32 dTCMLoadMode:1;
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UINT32 iTCMEnable:1;
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UINT32 iTCMLoadMode:1;
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UINT32 :12; // reserved
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}bits;
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UINT32 all;
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} arm946eControlRegU;
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extern arm946eControlRegU _arm946eControlReg_DS;
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// General IDs for read & write from CP15 registers
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#if defined (TTC_CORE_ARM946_CP15)
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typedef enum {
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ARM946E_CP15_CONTROL_REG = 0,
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ARM946E_CP15_DATA_CACHEABLE_REG,
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ARM946E_CP15_INST_CACHABLE_REG,
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ARM946E_CP15_DATA_BUFFERABLE_REG,
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ARM946E_CP15_DATA_ACCESS_PREMISSION_REG,
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ARM946E_CP15_INSTRUCTION_ACCESS_PREMISSION_REG,
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ARM946E_CP15_PROTECTION_REGION_0_REG,
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ARM946E_CP15_PROTECTION_REGION_1_REG,
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ARM946E_CP15_PROTECTION_REGION_2_REG,
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ARM946E_CP15_PROTECTION_REGION_3_REG,
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ARM946E_CP15_PROTECTION_REGION_4_REG,
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ARM946E_CP15_PROTECTION_REGION_5_REG,
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ARM946E_CP15_PROTECTION_REGION_6_REG,
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ARM946E_CP15_PROTECTION_REGION_7_REG,
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ARM946E_CP15_DATA_LOCKDOWN_CONTROL_REG,
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ARM946E_CP15_INST_LOCKDOWN_CONTROL_REG,
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ARM946E_CP15_DATA_TCM_REGION_REG,
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ARM946E_CP15_INST_TCM_REGION_REG,
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ARM946E_CP15_PID_REG,
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ARM946E_CP15_CACHE_DEBUG_INDEX_REG,
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ARM946E_CP15_INST_TAG_WRITE_REG,
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ARM946E_CP15_DATA_TAG_WRITE_REG,
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ARM946E_CP15_INST_CACHE_WRITE_REG,
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ARM946E_CP15_DATA_CACHE_WRITE_REG,
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ARM946E_CP15_CONTROL_CONFIGURATION_REG,
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ARM946E_CP15_PERFORMANCE_COUNTER_AP_REG,
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ARM946E_CP15_COPROCESSOR_ENABLE_REG,
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ARM946E_CP15_REGISTERS_NUM
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} EARM946ECP15Regs;
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#else
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typedef enum {
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ARM946E_CP15_ID_CODE_REG =0 ,
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ARM946E_CP15_CACHE_DETAILS_REG,
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ARM946E_CP15_TCM_SIZE_REG,
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ARM946E_CP15_CONTROL_REG,
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ARM946E_CP15_DATA_CACHEABLE_REG,
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ARM946E_CP15_INST_CACHABLE_REG,
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ARM946E_CP15_DATA_BUFFERABLE_REG,
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ARM946E_CP15_DATA_ACCESS_PREMISSION_REG,
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ARM946E_CP15_INSTRUCTION_ACCESS_PREMISSION_REG,
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ARM946E_CP15_PROTECTION_REGION_0_REG,
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ARM946E_CP15_PROTECTION_REGION_1_REG,
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ARM946E_CP15_PROTECTION_REGION_2_REG,
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ARM946E_CP15_PROTECTION_REGION_3_REG,
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ARM946E_CP15_PROTECTION_REGION_4_REG,
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ARM946E_CP15_PROTECTION_REGION_5_REG,
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ARM946E_CP15_PROTECTION_REGION_6_REG,
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ARM946E_CP15_PROTECTION_REGION_7_REG,
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ARM946E_CP15_FLUSH_INST_CACHE_REG,
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ARM946E_CP15_INVALIDATE_INST_CACHE_SINGLE_ENTRY_REG,
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ARM946E_CP15_PREFETCH_INST_CACHE_LINE_REG,
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ARM946E_CP15_FLUSH_DATA_CACHE_REG, /*20*/
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ARM946E_CP15_INVALIDATE_DATA_CACHE_SINGLE_ENTRY_REG,
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ARM946E_CP15_CLEAN_DATA_CACHE_ENTRY_REG,
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/*Added by AlexR 15.07.2004*/
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ARM946E_CP15_CLEAN_AND_FLASH_DATA_CACHE__ENTRY_REG,
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ARM946E_CP15_FLUSH_DATA_CACHE_SINGLE_ENTRY_INDEX_AND_SEGMENT_REG,
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ARM946E_CP15_CLEAN_DATA_CACHE_INDEX_AND_SEGMENT_ENTRY_REG,
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ARM946E_CP15_DRAIN_WRITE_BUFFER_REG,
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ARM946E_CP15_LOW_POWER_STATE_REG,
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ARM946E_CP15_DATA_LOCKDOWN_CONTROL_REG,
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ARM946E_CP15_INST_LOCKDOWN_CONTROL_REG,
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ARM946E_CP15_DATA_TCM_REGION_REG,
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ARM946E_CP15_INST_TCM_REGION_REG,
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ARM946E_CP15_PID_REG,
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ARM946E_CP15_TAG_BIST_CONTROL_REG,
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ARM946E_CP15_TCM_BIST_CONTROL_REG,
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ARM946E_CP15_CACHE_RAM_BIST_CONTROL_REG,
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ARM946E_CP15_INST_TAG_BIST_ADDR_REG,
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ARM946E_CP15_INST_TAG_BIST_GENERAL_REG,
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ARM946E_CP15_DATA_TAG_BIST_ADDR_REG,
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ARM946E_CP15_DATA_TAG_BIST_GENERAL_REG,
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ARM946E_CP15_INST_TCM_BIST_ADDR_REG,
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ARM946E_CP15_INST_TCM_BIST_GENERAL_REG,
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ARM946E_CP15_DATA_TCM_BIST_ADDR_REG,
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ARM946E_CP15_DATA_TCM_BIST_GENERAL_REG,
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ARM946E_CP15_INST_CACHE_RAM_BIST_ADDR_REG,
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ARM946E_CP15_INST_CACHE_RAM_BIST_GENERAL_REG,
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ARM946E_CP15_DATA_CACHE_RAM_BIST_ADDR_REG,
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ARM946E_CP15_DATA_CACHE_RAM_BIST_GENERAL_REG,
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ARM946E_CP15_TEST_STATE_REG,
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ARM946E_CP15_CACHE_DEBUG_INDEX_REG,
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ARM946E_CP15_INST_TAG_WRITE_REG,
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ARM946E_CP15_DATA_TAG_WRITE_REG,
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ARM946E_CP15_INST_CACHE_WRITE_REG,
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ARM946E_CP15_DATA_CACHE_WRITE_REG,
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ARM946E_CP15_TRACE_CONTROL_REG,
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ARM946E_CP15_DCACHE_LN_INVALIDATE_REG,
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ARM946E_CP15_REGISTERS_NUM
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} EARM946ECP15Regs;
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#endif
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// TCM load mode
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typedef enum{
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TCM_LOAD_MODE_DISABLE = 0,
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TCM_LOAD_MODE_ENABLE
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}ETCMLoadMode;
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typedef enum{
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TCM_DISABLE = 0,
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TCM_ENABLE
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}ETCMMode;
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typedef enum{
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CACHE_DISABLE = 0,
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CACHE_ENABLE
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}ECacheMode;
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typedef enum{
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VECTOR_SELECT_MODE0 = 0,
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VECTOR_SELECT_MODE1
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}EVectorSelectMode;
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typedef enum{
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LITTLE_ENDIAN =0,
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BIG_ENDIAN
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}EEndianConfiguration;
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typedef enum{
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PMU_DISABLE = 0,
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PMU_ENABLE
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}EPMUMode;
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#if defined (TTC_CORE_ARM946_CP15)
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typedef enum{
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BPU_DISABLE = 0,
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BPU_ENABLE
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}EBpuMode;
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#endif
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//Cache size definitions
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#define ARM946E_CACHE_SIZE_0K (0x0L) // (b0000)
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#define ARM946E_CACHE_SIZE_4K (0x3L) // (b0011)
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#define ARM946E_CACHE_SIZE_8K (0x4L) // (b0100)
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#define ARM946E_CACHE_SIZE_16K (0x5L) // (b0101)
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#define ARM946E_CACHE_SIZE_32K (0x6L) // (b0110)
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#define ARM946E_CACHE_SIZE_64K (0x7L) // (b0111)
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#define ARM946E_CACHE_SIZE_128K (0x8L) // (b1000)
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#define ARM946E_CACHE_SIZE_256K (0x9L) // (b1001)
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#define ARM946E_CACHE_SIZE_512K (0xAL) // (b1010)
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#define ARM946E_CACHE_SIZE_1M (0xBL) // (b1011)
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//TCM size definitions
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#define ARM946E_TCM_SIZE_0K (0x0L) // (b0000)
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#define ARM946E_TCM_SIZE_4K (0x3L) // (b0011)
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#define ARM946E_TCM_SIZE_8K (0x4L) // (b0100)
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#define ARM946E_TCM_SIZE_16K (0x5L) // (b0101)
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#define ARM946E_TCM_SIZE_32K (0x6L) // (b0110)
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#define ARM946E_TCM_SIZE_64K (0x7L) // (b0111)
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#define ARM946E_TCM_SIZE_128K (0x8L) // (b1000)
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#define ARM946E_TCM_SIZE_256K (0x9L) // (b1001)
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#define ARM946E_TCM_SIZE_512K (0xAL) // (b1010)
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#define ARM946E_TCM_SIZE_1M (0xBL) // (b1011)
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// Cache masks
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#define ARM946E_DATA_CACHE_SIZE_MASK (0x3C0000)
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#define ARM946E_INST_CACHE_SIZE_MASK (0x3C0)
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// Gernal control masks
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#define ARM946E_CONTROL_REG_AND_MASK (0xFF0DF)
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#define ARM946E_CONTROL_REG_OR_MASK (0x78)
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#define ARM946E_TCM_SZ_REG_AND_MASK (0xf)
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// General defines
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#define REGION_BASE_REGISTER_OFFSET (12)
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#define ITCM_SZ_REGISTER_OFFSET (6)
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#define DTCM_SZ_REGISTER_OFFSET (18)
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// Function prototypes
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//General functions
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UINT32 Arm946eCP15Read(UINT32 reg);
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UINT32 Arm946eCP15Write(UINT32 value,UINT32 reg);
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// Get...
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UINT32 Arm946eCP15GetIDCodeReg(void);
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UINT32 Arm946eCP15GetCacheTypeReg(void);
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UINT32 Arm946eCP15GetDataCacheSize(void);
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UINT32 Arm946eCP15GetInstructionCacheSize(void);
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UINT32 Arm946eCP15GetTCMSizeReg(void);
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UINT32 Arm946eCP15GetDataTCMSize(void);
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UINT32 Arm946eCP15GetInstTCMSize(void);
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UINT32 Arm946eCP15GetControlReg_DS(void);
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UINT32 Arm946eCP15GetControlReg_TCS(void);
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ETCMLoadMode Arm946eCP15GetInstTCMLoadMode(void);
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UINT32 Arm946eCP15GetInstTCMEnable(void);
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UINT32 Arm946eCP15GetDataTCMLoadMode(void);
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UINT32 Arm946eCP15GetDataTCMEnable(void);
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UINT32 Arm946eCP15GetInstCacheEnable(void);
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#if defined (TTC_CORE_ARM946_CP15)
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UINT32 Arm946eCP15GetBpuEnable(void);
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#endif
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UINT32 Arm946eCP15GetDataCacheEnable(void);
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UINT32 Arm946eCP15GetAlternateVectorSelect(void);
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UINT32 Arm946eCP15GetBigEndian(void);
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UINT32 Arm946eCP15GetMPUEnalbe_DS(void);
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UINT32 Arm946eCP15GetMPUEnalbe_TCS(void);
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UINT32 Arm946eCP15GetRegionBaseAndSizeReg(EMpuRegionsId region);
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UINT32 Arm946eCP15GetDataTCMRegionBaseAndSizeReg(void);
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UINT32 Arm946eCP15GetInstTCMRegionBaseAndSizeReg(void);
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// Set...
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UINT32 Arm946eCP15SetControlReg(UINT32 value);
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UINT32 Arm946eCP15SetInstTCMLoadMode(ETCMLoadMode loadMode);
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UINT32 Arm946eCP15SetInstTCMEnable_DS(void);
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UINT32 Arm946eCP15SetInstTCMEnable_TCS(void);
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UINT32 Arm946eCP15SetInstTCMDisable(void);
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UINT32 Arm946eCP15RestoreInstTCMEnable(ETCMMode oldITcmEnableMode);
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UINT32 Arm946eCP15RestoreDataTCMEnable(ETCMMode oldITcmEnableMode);
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UINT32 Arm946eCP15SetDataTCMLoadMode(ETCMLoadMode loadMode);
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UINT32 Arm946eCP15SetDataTCMEnable_DS(void);
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UINT32 Arm946eCP15SetDataTCMEnable_TCS(void);
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UINT32 Arm946eCP15SetDataTCMDisable(void);
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UINT32 Arm946eCP15SetInstCacheEnable_DS(void);
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UINT32 Arm946eCP15SetInstCacheEnable_TCS(void);
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UINT32 Arm946eCP15SetInstCacheDisable(void);
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UINT32 Arm946eCP15SetDataCacheEnable_DS(void);
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UINT32 Arm946eCP15SetDataCacheEnable_TCS(void);
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UINT32 Arm946eCP15SetDataCacheDisable(void);
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UINT32 Arm946eCP15SetAlternateVectorSelect(EVectorSelectMode vectorSelectMode);
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UINT32 Arm946eCP15SetBigEndian(EEndianConfiguration endianMode);
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UINT32 Arm946eCP15SetMPUEnalbe_DS(void);
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UINT32 Arm946eCP15SetMPUEnalbe_TCS(void);
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UINT32 Arm946eCP15SetMPUDisable_DS(void);
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UINT32 Arm946eCP15SetMPUDisable_TCS(void);
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UINT32 Arm946eCP15RestoreMPUEnableDisable_DS(UINT32 enableDisable);
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UINT32 Arm946eCP15RestoreMPUEnableDisable_TCS(UINT32 enableDisable);
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UINT32 Arm946eCP15SetRegionAccessPermission_DS(EMpuRegionsId region,CMpuRegionAttributes attribute);
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UINT32 Arm946eCP15SetRegionAccessPermission_TCS(EMpuRegionsId region,CMpuRegionAttributes attribute);
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UINT32 Arm946eCP15SetRegionBaseAndSizeReg_DS(EMpuRegionsId region,UINT32 baseAddress,UINT32 regionSize,EMpuRegionMode regionEnableDisable);
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UINT32 Arm946eCP15SetRegionBaseAndSizeReg_TCS(EMpuRegionsId region,UINT32 baseAddress,UINT32 regionSize,EMpuRegionMode regionEnableDisable);
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UINT32 Arm946eCP15FlushInstCache(void);
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UINT32 Arm946eCP15FlushDataCache(void);
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UINT32 Arm946eCP15DrainWriteBuffer(void);
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UINT32 Arm946eCP15SetLowPowerState(void);
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UINT32 Arm946eCP15SetDataTCMRegionBaseAndSizeReg_DS(UINT32 areaSize,UINT32 regionBase);
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UINT32 Arm946eCP15SetDataTCMRegionBaseAndSizeReg_TCS(UINT32 areaSize,UINT32 regionBase);
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UINT32 Arm946eCP15SetInstTCMRegionBaseAndSizeReg_DS(UINT32 areaSize,UINT32 regionBase);
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UINT32 Arm946eCP15SetInstTCMRegionBaseAndSizeReg_TCS(UINT32 areaSize,UINT32 regionBase);
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UINT32 Arm946eCP15DCacheLineInvalidReg(UINT32 Addr);
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UINT32 asm_Arm9ReadCP15_DS (UINT32 add_r0);
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UINT32 asm_Arm9ReadCP15_TCS (UINT32 add_r0);
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UINT32 asm_Arm9WriteCP15_DS (UINT32 val_r0 ,UINT32 add_r1);
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UINT32 asm_Arm9WriteCP15_TCS(UINT32 val_r0 ,UINT32 add_r1);
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#if defined (TTC_CORE_ARM946_CP15)
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UINT32 Arm946eCP15GetBpuEnable(void);
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UINT32 Arm946eCP15SetBpuEnable(void);
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UINT32 Arm946eCP15SetBpuDisable(void);
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UINT32 asm_arm946e_InvalidateInsCacheFlushBPU(void);
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UINT32 asm_arm946e_FlushDCache(void);
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UINT32 asm_arm946e_DrainBuffers(void);
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UINT32 asm_arm946e_WaitForInterruptLowPower(void);
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void Arm946eCP15FlushCleanDcacheIcache(void);
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UINT32 asm_arm946e_ReadIDCode(void);
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UINT32 asm_arm946e_ReadCacheType(void);
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UINT32 asm_arm946e_ReadTCMSize(void);
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void asm_arm946e_CleanInvalidateDCacheAll(void);
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#endif
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void InvalidateDataCache(UINT32 address, UINT32 size);
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#endif //ARM946E_SCP15_H
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