114 lines
4.2 KiB
C
114 lines
4.2 KiB
C
/*--------------------------------------------------------------------------------------------------------------------
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(C) Copyright 2006, 2007 Marvell DSPC Ltd. All Rights Reserved.
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-------------------------------------------------------------------------------------------------------------------*/
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/*********************************************************************
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* M O D U L E B O D Y *
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**********************************************************************
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* Title: Direct Memory Access - DMA *
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* *
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* Filename: dma_hw_connectivity.h *
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* *
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* Target, platform: Arbel Platform, Tavor *
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* *
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* Author: Olga Fomenko *
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* *
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* Description: This is the HARDWARE file header for the DMA pacakge. *
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* It contains connectivity tables - system definitions. *
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* Notes: CURRENT STATUS - TBD !!!! *
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**********************************************************************
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*/
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#ifndef _DMA_HW_CONNECTIVITY_H_
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#define _DMA_HW_CONNECTIVITY_H_
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#include "intc_list.h"
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#include "global_types.h"
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typedef enum
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{
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// DMAC1
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DMA_CHANNEL_0 = 0x00,
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DMA_CHANNEL_1 = 0x01,
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DMA_CHANNEL_2 = 0x02,
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DMA_CHANNEL_3 = 0x03,
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DMA_CHANNEL_4 = 0x04,
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DMA_CHANNEL_5 = 0x05,
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DMA_CHANNEL_6 = 0x06,
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DMA_CHANNEL_7 = 0x07,
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DMA_CHANNEL_8 = 0x08,
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// DMAC2
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DMA_CHANNEL_9 = 0x09,
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DMA_CHANNEL_10 = 0x0A,
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DMA_CHANNEL_11 = 0x0B,
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DMA_CHANNEL_12 = 0x0C,
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DMA_CHANNEL_13 = 0x0D,
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DMA_CHANNEL_14 = 0x0E,
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DMA_CHANNEL_15 = 0x0F,
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//#ifndef PHS_SW_DEMO_TTC
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// DMAC3
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DMA_CHANNEL_16 = 0x10,
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DMA_CHANNEL_17 = 0x11, // disable tbd
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DMA_CHANNEL_18 = 0x12,
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DMA_CHANNEL_19 = 0x13,
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DMA_CHANNEL_20 = 0x14,
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DMA_CHANNEL_21 = 0x15,
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DMA_CHANNEL_22 = 0x16,
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DMA_CHANNEL_23 = 0x17
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//#endif
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}DMA_ChannelE;
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typedef enum
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{
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DMA_DREQCHANNEL0 = 0,
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DMA_DREQCHANNEL1,
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DMA_DREQCHANNEL2,
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DMA_DREQCHANNEL3,
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DMA_DREQCHANNEL4,
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DMA_DREQCHANNEL5,
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DMA_DREQCHANNEL6,
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DMA_DREQCHANNEL7,
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DMA_DREQDEFAULT = 0xFF
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}DMA_DREQConnectionE;
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typedef enum
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{
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DMA_MUXCONNECTION_0 = 0x00,
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DMA_MUXCONNECTION_1 = 0x01,
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DMA_MUXCONNECTION_2 = 0x02,
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DMA_MUXCONNECTION_3 = 0x03,
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DMA_MUXDEFAULT = 0xFF
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}DMA_MUXConnectionE;
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typedef struct
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{
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BOOL isChannelAvailable;
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INTC_InterruptSources interruptConnection;
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DMA_DREQConnectionE dreqConnection;
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}DMA_ConnectivityS;
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#define DMA_NUMBER_OF_DEVICES 8
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#define DMA_CHANNEL_DTCM_2_DTCM DMA_CHANNEL_16
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#define DMA_CHANNEL_DTCM_2_DDR DMA_CHANNEL_18
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//#define DMA_CDMA1_MUX_REGISTER_INIT_VALUE = 0x0 // configured by MSA
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#ifdef PHS_SW_DEMO_TTC
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#define DMA_CDMA2_MUX_REGISTER_INIT_VALUE 0x5004 // shared reg (Arbel and MSA), configured by Arbel driver
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#else
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#define DMA_CDMA2_MUX_REGISTER_INIT_VALUE 0x2000 // shared reg (Arbel and MSA), configured by Arbel driver
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#define DMA_CDMA3_MUX_REGISTER_INIT_VALUE 0x0880 // Belongs to Arbel only
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#endif
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extern INTC_InterruptSources _dmaInterruptConnectivityTable[];
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extern DMA_DREQConnectionE _dmaDREQConnection[];
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extern BOOL _dmaIsChannelAvailableTable[];
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extern UINT8 _dmaConnectExternalMuxDREQLegality[];
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extern UINT8 _dmaPortDirection[][DMA_NUMBER_OF_DEVICES];
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extern UINT8 _dmaExternalMuxConnection[];
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#endif //_DMA_HW_CONNECTIVITY_H_
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