118 lines
5.9 KiB
C
118 lines
5.9 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*--------------------------------------------------------------------------------------------------------------------
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INTEL CONFIDENTIAL
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Copyright 2006 Intel Corporation All Rights Reserved.
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The source code contained or described herein and all documents related to the source code ("Material") are owned
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by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or
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its suppliers and licensors. The Material contains trade secrets and proprietary and confidential information of
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Intel or its suppliers and licensors. The Material is protected by worldwide copyright and trade secret laws and
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treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted,
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transmitted, distributed, or disclosed in any way without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual property right is granted to or
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conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement,
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estoppel or otherwise. Any license under such intellectual property rights must be express and approved by
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Intel in writing.
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-------------------------------------------------------------------------------------------------------------------*/
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/************************************************************************/
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/* */
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/* Title: UART config header file */
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/* */
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/* Filename: UART_config.h */
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/* */
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/* Author: Shirley Elbling */
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/* */
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/* Target, subsystem: Common Platform, HAL */
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/* */
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/************************************************************************/
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/* name of macro include an extra underscore since Hermon SW already include the same macro name */
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#ifndef _UART_CONFIG_H__
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#define _UART_CONFIG_H__
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/* MEGA-SWITCHES:
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- THIS FILE: SILICON_TTC, _HERMON_B0_SILICON_, INTEL_2CHIP_PLAT_BVD, _TAVOR_BOERNE_, _TAVOR_HARBELL_
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- MAKE: none
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*/
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#include "syscfg.h"
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#if defined(_HERMON_B0_SILICON_) || defined(_TAVOR_BOERNE_) || defined(INTEL_2CHIP_PLAT_BVD)
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// GPIO wakeup feature allows to shutdown the UART clocks and use the GPIO edge detectors to
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// wake the driver up when activity is detected on one of the input lines (RX,RTS,DCD...)
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// This requires access to GPIO module and pin-mux.
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#define UART_GPIO_WAKEUP_FEATURE
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#endif
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//#if defined(_TAVOR_HARBELL_) || defined(SILICON_TTC) || defined(SILICON_PV2)
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#if defined(SILICON_TTC) || defined(SILICON_PV2)
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// The driver supports one port only (otherwise 3 ports known as FF,BT,ST uarts - legacy names).
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// On Tavor COM-side only one UART is available
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// On TTC one compatible UART is available (intended for COM use). The two other ports are new and are not yet supported.
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#define UART_SINGLE_PORT
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#endif
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//#if defined(_TAVOR_HARBELL_) || defined(SILICON_PV2)
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#if defined(SILICON_PV2)
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// UART registers do not retain state in sleep (D2): special care is required to backup and restore the values.
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#define UART_D2_SPECIFIC
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#define INTC_CONFIGURE_WITH_3_ARGUMENTS
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#endif
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#if defined(_HERMON_B0_SILICON_) && !defined(_TAVOR_BOERNE_)
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// Modem signals control (DCD, RI) is supported in UART API but is implemented on Hermon only.
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#define UART_MODEM_SIGNAL_CONTROL
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#endif
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//#if defined(_TAVOR_HARBELL_) || defined(SILICON_PV2)
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#if defined(SILICON_PV2)
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// A dedicated interrupt is generated to signal UART wakeup: supported only on Tavor - Harbell UART.
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#define UART_WAKEUP_INT INTC_CRXD_32_28_EVENT
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#endif
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//#if !defined(_TAVOR_HARBELL_) || defined(SILICON_PV2)
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#if 1
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// UART module output to the interrupt controller is level: clear by either IIR read or RHR/MCR access depending on interrupt type
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// Harbell case: it is clear the interrupt is level; however, leave the "legacy" BUG until confirmed
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#define UART_INTERRUPT_IS_LEVEL
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#endif
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#if defined(_HERMON_B0_SILICON_) || defined(_TAVOR_BOERNE_)
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// UART may issue spurious interrupts (interrupt pending while IIR indicates no interrupt).
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// In this case:
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// 1) If LSR indicates there's data in RX FIFO: read as normal RX data
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// 2) Otherwise, dummy-read RHR to clear
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#define UART_SPURIOUS_INT_RHR_READ_WA
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// UART Si bug w/a: it is prohibited to read IIR UNLESS a UART interrupt is really pending: 1188494
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#define UART_IIR_READ_ONLY_WHEN_PENDING
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#endif
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#if !defined (_QT_)
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// Normal UART clock rate: this clock setting is out of scope of UART driver.
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#define UART_CLOCK 14745600L /* the UART clock Hz input clock */
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#else
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#if defined(_HERMON_B0_SILICON_) && !defined(_TAVOR_BOERNE_)
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// SLE (QT), Hermon: SLE clock corresponds to 312MHz (PLL highest rate)
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#define UART_CLOCK 12320L /* the UART clock Hz input clock for Hermon */
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#else
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// SLE (QT): SLE clock corresponds to 624MHz (PLL highest rate)
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// PLEASE, ADD MORE DETAILS ABOUT THE CALCULATION
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#define UART_CLOCK 7040L /* the UART clock Hz input clock for Tavor*/
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#endif
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#endif //QT
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// UART peripheral base addresses
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#define UART_BASE_ADDRESS 0xD4010000 /* the base addres of harbel uart */
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#define STUART_OFFSET 0x8000 /* the offset of Slow UART */
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#define FFUART_OFFSET 0x7000
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#define BTUART_OFFSET 0xF000
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#define U4UART_OFFSET 0xF800
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#endif /* _INTC_CONFIG_H_ */
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