305 lines
9.6 KiB
C
305 lines
9.6 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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//Copyright 2005, Intel Corporation, All rights reserved.
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/************************************************************************/
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/* Utils.h - */
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/* */
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/************************************************************************/
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#ifndef _UTILS_H_
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#define _UTILS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "global_types.h"
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//should be used in BootLoader & Flasher ONLY
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//#define LOW_LEVEL_ASSERTS_ONLY
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//#if defined (_TAVOR_HARBELL_) || defined(SILICON_PV2)
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#if defined(SILICON_PV2)
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// To Be Deleted...
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#define Manitoba_Create_HISR Os_Create_HISR /*currently refered from diag_comm_SSP.c. Correct reference should be bsp_hisr.h*/
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#endif
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typedef enum
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{
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CPU_HERMON_B0 = 0,
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CPU_HERMON_B1,
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CPU_HERMON_B2,
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CPU_HERMON_B3,
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CPU_HERMON_TCB874,
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CPU_HERMONL_A0,
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CPU_HERMONC_A0,
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CPU_HERMON_TCC874,
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CPU_HERMONEL_A0,
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CPU_MANITOBA_OTHER,
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CPU_BVD,
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CPU_TAVOR_A0,
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CPU_TAVOR_B0,
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CPU_TAVOR_B1,
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CPU_TAVOR_B2,
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CPU_TAVOR_PV_A0,
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CPU_TAVOR_PV_B0,
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CPU_TAVOR_PV_C0,
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CPU_TTC,
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CPU_OTHER
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}CPU_Version; //if this enum changed, update also the CPU_Version_str[]
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// Returns the CPU version according to the above list
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CPU_Version GetCpuVersion(void);
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typedef enum CPU_family_tag
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{
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CPU_TAVOR_PV2, //Z0, A0, B0
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CPU_TAVOR_MG1, // Z0=A0, A1, B0
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CPU_TAVOR_MG2, // A0
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CPU_ESHEL, // A0
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CPU_NEVO, // A0
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CPU_ESHEL_LTE, // A0
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CPU_FAMILY_UNKN
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}CPU_family;
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CPU_family GetCpuFamily(void);
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// Returns the original CPSR
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// exp: old_level = disableInterrupts();
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// old_level MUST be local automatic variable !!
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unsigned long disableInterrupts(void);
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// Returns the original CPSR
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// exp: old_level = enableInterrupts();
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// old_level MUST be local automatic variable !!
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unsigned long enableInterrupts(void);
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// Restores the IF bits in the CPSR to that value of the CPSR passed.
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// The latter should be obtained from the enable/disable functions
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// exp: restoreInterrupts(old_level);
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// old_level MUST be local automatic variable !!
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void restoreInterrupts(unsigned long ir);
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// Count Leading Zeros
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// Returns: 0 for 0x8xxxxxxx; 1 for 0x04xxxxxx; 31 for 0x00000001; 32 for 0
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int _clz(unsigned long x);
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// revert
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// Returns: reverted endian value.change the order of bytes in the 32bit parameter from big to little endian and vice versa.
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unsigned long _rev(unsigned long x);
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// CP14 functions
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void _xsFreqChange(void);
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// Enter idle mode
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void _xsGoIdle(void); //just idle the Xscale core
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void setIdle(void); //same as previous
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void setIdleExt(UINT32 newXPCR, UINT32 oldXPCR); //idle the core with shutting down the MEMC and modifying PMU.XPCR
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//
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// General: soft-restart the image
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//
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void doRestart(void);
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// Function analog of ASSERT
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void fatalError(int condition);
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// Assert macros
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#ifndef LOW_LEVEL_ASSERTS_ONLY
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extern void utilsAssertFail(const char *cond,
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const char *file,
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signed short line,
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unsigned char allowDiag);
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//regular ASSERTs
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#if defined __MODULE__
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#define WARNING(cOND) { if (!(cOND)) { utilsAssertFail(NULL , __MODULE__, __LINE__, 0xFF); } }
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#define ASSERT(cOND) { if (!(cOND)) { utilsAssertFail(NULL, __MODULE__, __LINE__, 1); } }
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#else
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#define WARNING(cOND) { if (!(cOND)) { utilsAssertFail(NULL , __FILE__, __LINE__, 0xFF); } }
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#define ASSERT(cOND) { if (!(cOND)) { utilsAssertFail(NULL, __FILE__, __LINE__, 1); } }
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#endif
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#define ASSERT_NO_DIAG(cOND) { if (!(cOND)) { utilsAssertFail(NULL, __FILE__, __LINE__, 0); } }
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#else//LOW_LEVEL_ASSERTS_ONLY
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/*Make ALL ASSERTS as ASSERT_LOW_LEVEL*/
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#define WARNING(cOND) /*WARNING*/
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#define ASSERT(cOND) {ASSERT_LOW_LEVEL(cOND,0xAA)}
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#define ASSERT_NO_DIAG(cOND) {ASSERT_LOW_LEVEL(cOND,0xAA)}
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#endif /*LOW_LEVEL_ASSERTS_ONLY*/
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#define ASSERT_LOW_LEVEL(cOND,vALUE) {\
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if (!(cOND)) \
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{ \
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disableInterrupts(); \
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while (1);\
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} \
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}
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#define fatalError(number) ASSERT(FALSE)
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#define inbyte(addr) (*((volatile UINT8 *)addr))
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#define inword(addr) (*((volatile UINT16 *)addr))
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#define inlong(addr) (*((volatile UINT32 *)addr))
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#define outbyte(addr,val) (*((volatile UINT8 *)addr)=(UINT8)val)
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#define outword(addr,val) (*((volatile UINT16 *)addr)=(UINT16)val)
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#define outlong(addr,val) (*((volatile UINT32 *)addr)=(UINT32)val)
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//
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// CP14: Performance monitoring unit access
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//
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// Read/Set PMNC (Control Register, see Elkart core EAS chapter 8)
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// Here are the bit definitions:
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#define PMNC_ALL_ENABLE 1
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#define PMNC_ALL_RESET 2
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#define PMNC_CCNT_RESET 4
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#define PMNC_CCNT_DIV64 8
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#define PMNC_STOP_MASK 0xFFFFFFF0 //Stop all counters
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#define PMNC_RESTR_MASK 0xFFFFFFE7 //Enable all counters+reset CCNT and Performance regs
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#define PMNC_START_MASK 0xFFFFFFE1 //Enable all clocks without reseting clk
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#define PMNC_ID_MASK 0xFF000000 /* Returns 0x14 for Elkart */
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void cp14SetPMNC(UINT32 value);
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UINT32 cp14ReadPMNC(void);
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// Read the Clock Counter register (core clock or same/64 depending on the PMNC_CCNT_DIV64 bit - below)
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UINT32 cp_ReadCCNT(void); // NEW generic name. OLD & NEW are aliased
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UINT32 cp14ReadCCNT(void); // OLD non-generic name, to be obsolete.
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UINT32 cp14SetCCNT(UINT32 value);
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UINT32 cp14ReadEVTSEL(void);
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void cp14SetEVTSEL(UINT32 value);
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UINT32 getCpRateKHz(void); // returns CP-counter rate in kHz or 0-unknown/default. Depends upon Core frequency
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//
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// CP6: WS Primary INTC co-processor bus access
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//
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UINT32 cp6ReadICPR(void);
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UINT32 cp6ReadICIP(void);
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UINT32 cp6ReadICFP(void);
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UINT32 cp6ReadICHP(void);
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UINT32 cp6ReadICMR(void);
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void cp6WriteICMR(UINT32 value);
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#define TOGGLE_REG_SET_BITS_ON(r, b) ((r) = ~(r)&(b))
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#define TOGGLE_REG_SET_BITS_OFF(r, b) ((r) &= (b))
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#define ARE_BITS_ON(r,b) ((b) == ((r)&(b)))
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#define ARE_BITS_OFF(r,b) (0x0 == ((r)&(b)))
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//#if defined (_TAVOR_HARBELL_)|| defined(SILICON_PV2)
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#if defined(SILICON_PV2)
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//ON-CHIP trace buffer is not supported on TAVOR A0 but on B0 only with JTAG protocol
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// Let's put macro-stubs meanwhile
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#define EnableTraceBuffer(vOID) /**/
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#define DisableTraceBuffer(vOID) /**/
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#define ReadTraceBuffer(pBUFFER) pBUFFER = NULL
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//#define ReadTBREG(x) 0
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//#define ReadCHKPT1(x) 0
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//#define ReadCHKPT0(x) 0
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#else
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/* XSCALEs*/
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// Add Tavor_Boerne interrupts Coprocessor access - it has 52 interrupts (and not only 32)
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UINT32 cp6ReadICPR2(void);
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UINT32 cp6ReadICIP2(void);
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UINT32 cp6ReadICFP2(void);
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UINT32 cp6ReadICMR2(void);
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void cp6WriteICMR2(UINT32 value);
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void EnableTraceBuffer(void);
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void DisableTraceBuffer(void);
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void ReadTraceBuffer(UINT32 *Buffer);
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UINT8 ReadTBREG(void);
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UINT32 ReadCHKPT1(void);
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UINT32 ReadCHKPT0(void);
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#endif//_TAVOR_HARBELL_ /* XSCALE only */
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// CPSR mode
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#define CPSR_MODE_BITS 0x1F
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#define CPSR_MODE_USER 0x10
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#define CPSR_MODE_FIQ 0x11
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#define CPSR_MODE_IRQ 0x12
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#define CPSR_MODE_SVC 0x13
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#define CPSR_MODE_ABT 0x17
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#define CPSR_MODE_UND 0x1B
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#define CPSR_MODE_SYS 0x1F
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#define CPSR_T_BIT 0x20 //Thumb
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#define CPSR_IRQ_BIT 0x80 // IRQ enable
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#define CPSR_FIQ_BIT 0x40 // IRQ enable
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UINT32 ReadSP(void);
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UINT32 Read_SPSR(void);
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UINT32 ReadCPSR(void);
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UINT32 ReadMode_R13(UINT32 mode);
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UINT32 ReadMode_R14(UINT32 mode);
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#ifdef LWIP_IPNETBUF_SUPPORT
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void SetSPAddress(UINT32 address);
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#endif
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// Set SP for the CPU mode specified by CPSR
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void SetMode_R13(UINT32 mode, UINT32 sp);
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// Set SP and SL (v7) for the current CPU mode
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void SetSystemStack(UINT32 sp, UINT32 limit);
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// Reads the r0-r14,pc,cpsr values into the given buffer (see EE_RegInfo_Data_t)
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void ReadRegisterContext(UINT32* pBuffer);
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// Restores r0-r13,pc,cpsr values from the given buffer (see EE_RegInfo_Data_t)
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// LR is not restored!
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// Jumps to pBuffer->PC
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void RestoreRegisterContext(UINT32* pBuffer);
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// Restores r0-r12 values from the given buffer (see EE_RegInfo_Data_t)
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// r13, LR, CPSR are not restored!
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// Returns from exception mode and jumps to pBuffer->PC
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void RestoreRegisterContextEx(UINT32* pBuffer, UINT32 setExcModeSP);
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//#if !defined (_TAVOR_HARBELL_) && !defined(SILICON_PV2) /* XSCALE only */
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#if !defined(SILICON_PV2) /* XSCALE only */
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//read ICAM/OCAM register
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//register_index what ICAMs to read READ: CRR[0..2]:
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//returns ICAM/OCAM register value
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UINT32 mcpComRead(UINT32 register_index);
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//
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// DEBUG CAPABILITIES ACCESS
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//
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void dbgSetIBCR0(UINT32 value);
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UINT32 dbgReadIBCR0(void);
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void dbgSetIBCR1(UINT32 value);
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UINT32 dbgReadIBCR1(void);
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void dbgSetDBR0(UINT32 value);
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UINT32 dbgReadDBR0(void);
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void dbgSetDBR1(UINT32 value);
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UINT32 dbgReadDBR1(void);
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void dbgSetDBCON(UINT32 value);
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UINT32 dbgReadDBCON(void);
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void dbgSetDCSR(UINT32 value);
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UINT32 dbgReadDCSR(void);
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#endif//_TAVOR_HARBELL_ /* XSCALE only */
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void doTurboFrequencyChange(UINT32 fBit,UINT32 tBit);
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UINT32 GetTurboFrequencyChangeCfgBits(void *pRegAddress);
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UINT32 RunOperationUnderSpecificStack_ASM(void *pFuncAddress,void *pStackAddress, UINT32 funcParam1);
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#ifdef __cplusplus
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}
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#endif
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#endif // _UTILS_H_
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