69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
#ifndef PERIPH_PSRAM_H
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#define PERIPH_PSRAM_H
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#include "syscall-arom.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* craneg not support clk mode, but bit8 reserved */
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typedef enum {
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CLK_MODE_1X = 0, /* 1x mode */
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CLK_MODE_2X, /* 2x mode */
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CLK_MODE_MAX
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} clk_mode_t;
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/*
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* PHYCLK clk select , bit20~18
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* craneg: phy clk = phy_sel/(phy_clk_divider+1), eg: phy clk = phy_sel/2 = 156/2=78M
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* craneLR A0/cranew cr5: phy clk = phy_sel/(phy_clk_divider+1)/clk_mode. clk_mode=1(1xmode), clk_mode=2(2xmode),
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* psram two edge samples, so Mbps = MHz *2;
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* If mcu is 208MHz, means it is 416Mbps(PSRAM_FREQ_416M).
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* PSRAM_FREQ_156Mbps: phy clk 78MHz
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*/
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struct PsramPP_t {
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unsigned freq;
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unsigned clkSel; /*clock selection ( pc clk select: bit28~26, phy clk select: bit20~18,) */
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unsigned clkDiv; /*phy clk divider (bit17~16) */
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clk_mode_t clkMode; /*0: 1x mode; 1: 2xmode, add after craneLR, include cranew cr5 */
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};
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#define PSRAM_FREQ_156M 0 /*LV0: 78M 156Mps*/
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#define PSRAM_FREQ_312M 1 /*LV1: 156M 312Mps*/
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#define PSRAM_FREQ_350M 2 /*LV2: 175M 350Mbps, craneLR: 356Mbps */
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#define PSRAM_FREQ_416M 3 /*LV3: 208M 416Mps*/
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#define PSRAM_FREQ_500M 4 /*LV4: 250M 500Mps*/
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#if 0
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//test lower freq can use it
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#define PSRAM_FREQ_LV4 4 /*LV4: */
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#define PSRAM_FREQ_LV5 5 /*LV5: */
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#endif
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/*
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* preboot will not use psram LV4 PSRAM_FREQ_533M, cp use LV4.
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* phy clk 533M ~2000M need enable PLL2, see Asic code: psram_fc_init -> phy_pll2_fc
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*/
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/*PCCLK clk select , bit28~26 */
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#define PSRAM_PCCLK_PLL1_312M 0
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#define PSRAM_PCCLK_PLL1_350M 1
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#define PSRAM_PCCLK_PLL1_416M 2
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#define PSRAM_PCCLK_PLL1_208M 4
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#define PSRAM_PCCLK_PLL1_156M 5
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#define PSRAM_CACHELINE_64B 0
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#define PSRAM_CACHELINE_128B 1
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#define PSRAM_CACHELINE_256B 2
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#define PSRAM_CACHELINE_512B 3
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void psram_init(void);
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void psram_pll1_enable(void);
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void psram_test(void);
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void psram_phy_fc_config(unsigned phyclk_level);
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_PSRAM_H */
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/** @} */
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