140 lines
5.2 KiB
C
140 lines
5.2 KiB
C
#ifndef _EFUSE_H
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#define _EFUSE_H
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* define fuse value for psram devie
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* PSRAM Type Code:
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* AP 16M 00000
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* Winbond 16M 00001
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* AP 8M + 8M 00010
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* Winbond 8M + 8M 00100
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* AP 8M 00101
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* Winbond 8M 00110
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* Winbond 250MHz 8M 00111
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* AP UHS 8M + UHS 8M 01000
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* Winbond 250MHz 8M + 250MHz 8M 01001
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*/
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#define AP_16M 0
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#define WB_16M 1
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#define AP_8M8M 2
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#define UNIIC_16M 3
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#define WB_8M8M 4
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#define AP_8M 5
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#define WB_8M 6
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#define WB_250MHZ_8M 7
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#define AP_UHS_8M8M 8
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#define WB_250MHZ_8M8M 9
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#define AP_250MHZ_8M8M 10
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#define WB_XCCELA_8M 11
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#define WB_XCCELA_8M8M 12
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#define WB_4M 13
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#define AP_4M 14
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#define WB_XCCELA_4M 15
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#define AP_250MHZ_8M 16
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#define WB_32M 17
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#define AP_250MHZ_16M 18
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#define WB_250MHZ_16M 19
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#define UNIIC_4M 20
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#define GD_4M 21
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#define GD_8M 22
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#define WB_8M_HYPER21 23
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#define WB_8M8M_HYPER21 24
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typedef enum {
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NO_PHY_AP_4M, /* 0 */
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NO_PHY_WB_4M, /* 1 */
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NO_PHY_AP_8M, /* 2 */
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NO_PHY_WB_8M, /* 3 */
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NO_PHY_AP_16M, /* 4 */
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NO_PHY_WB_16M, /* 5 */
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NO_PHY_UNIIC_16M, /* 6 */
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NO_PHY_UNIIC_4M, /* 7 */
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NO_PHY_PSRAM_TYPE_MAX /* 8 */
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} NO_PHY_PSRAM_TYPE_T;
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#define AP_16M_NAME "AP_16M" /* 0 */
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#define WB_16M_NAME "WB_16M" /* 1 */
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#define AP_8M8M_NAME "AP_8M8M" /* 2 */
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#define UNIIC_16M_NAME "UNIIC_16M" /* 3 */
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#define WB_8M8M_NAME "WB_8M8M" /* 4 */
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#define AP_8MB_NAME "AP_8M" /* 5 */
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#define WB_8MB_NAME "WB_8M" /* 6 */
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#define WB_250MHZ_8M_NAME "WB_250MHZ_8M" /* 7 */
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#define AP_UHS_8M8M_NAME "AP_UHS_8M8M" /* 8 */
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#define WB_250MHZ_8M8M_NAME "WB_250MHZ_8M8M" /* 9 */
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#define AP_250MHZ_8M8M_NAME "AP_250MHZ_8M8M" /* 10 */
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#define WB_XCCELA_8M_NAME "WB_XCCELA_8M" /* 11 */
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#define WB_XCCELA_8M8M_NAME "WB_XCCELA_8M8M" /* 12 */
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#define WB_4MB_NAME "WB_4M" /* 13 */
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#define AP_4MB_NAME "AP_4M" /* 14 */
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#define WB_XCCELA_4M_NAME "WB_XCCELA_4M" /* 15 */
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#define AP_250MHZ_8M_NAME "AP_250MHZ_8M" /* 16 */
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#define WB_32M_NAME "WB_32M" /* 17 */
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#define AP_250MHZ_16M_NAME "AP_250MHZ_16M" /* 18 */
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#define WB_250MHZ_16M_NAME "WB_250MHZ_16M" /* 19 */
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#define UNIIC_4M_NAME "UNIIC_4M" /* 20 */
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#define GD_4M_NAME "GD_4M" /* 21 */
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#define GD_8M_NAME "GD_8M" /* 22 */
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/* 3660 CR5 boot by mcu, not in preboot, preboot only read psram type for scrtach reg, and set prop */
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#define WB_8M_HYPER21_NAME "WB_8M_HYPER21" /* 23 */
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#define WB_8M8M_HYPER21_NAME "WB_8M8M_HYPER21" /* 24 */
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/* psram_crane_mcu.h defined psram type id instead of efuse.h */
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#define AP256Mb_1_2V_X16_CS0_NAME "AP256Mb_1_2V_X16_CS0" /* 0 */
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#define AP256Mb_1_2V_X16_CS1_NAME "AP256Mb_1_2V_X16_CS1" /* 1 */
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#define AP256Mb_1_2V_X16_CS0_CS1_NAME "AP256Mb_1_2V_X16_CS0_CS1" /* 2 */
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#define WB256Mb_1_8V_X16_CS0_NAME "WB256Mb_1_8V_X16_CS0" /* 3 */
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#define WB256Mb_1_8V_X16_CS1_NAME "WB256Mb_1_8V_X16_CS1" /* 4 */
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#define WB256Mb_1_8V_X16_CS0_CS1_NAME "WB256Mb_1_8V_X16_CS0_CS1" /* 5 */
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#define PSRAM_SIZE_4M 0x400000
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#define PSRAM_SIZE_8M 0x800000
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#define PSRAM_SIZE_16M 0x1000000
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#define PSRAM_SIZE_32M 0x2000000
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/* software defined ddr type, can diff with fuse value for ddr device:
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* DDR Type Code:
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* CraneGT use DDR， connect flash instead of SIP
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* 3605S： DDR 32MB + Nor flash 16MB
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* 3605E： DDR 64MB + Nand flash 64MB
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*/
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typedef enum {
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DRAM_AP_32M, /* 0 / * 3605S-111 * / */
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DRAM_UniIC_32M, /* 1 / * 3605S-110 * / */
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DRAM_AP_64M, /* 2 / * 3605E-110 * / */
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DSRAM_TYPE_MAX /* 3 */
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} DRAM_TYPE_T;
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#define DRAM_AP_32M_NAME "DRAM_AP_32M" /*Bytes */
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#define DRAM_AP_64M_NAME "DRAM_AP_64M"
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#define DRAM_UniIC_32M_NAME "DRAM_UniIC_32M"
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#define DRAM_UniIC_64M_NAME "DRAM_UniIC_64M"
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/* reversed fuse ddr bits, but not use fuse now, use autodetect */
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#define DRAM_SIZE_32M 0x2000000
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#define DRAM_SIZE_64M 0x4000000
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#define DRAM_SIZE_128M 0x8000000
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unsigned int efuse_get_psram_version(void);
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unsigned efuse_cranew_mcu_psram(void);
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unsigned int get_psram_size(void);
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unsigned int get_ddr_size(void);
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void fuse_read_lotid(void);
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int fuse_trust_boot_enabled(void);
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bool is_chip_support_auto_detect(void);
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bool efuse_modem_type_is_radio(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _EFUSE_H */
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/** @} */
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