558 lines
21 KiB
C
558 lines
21 KiB
C
#include "efuse.h"
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#include "reg.h"
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#include <stdio.h>
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#include <string.h>
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#include "property.h"
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#include "cpu.h"
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#include "pmu.h"
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#include "log.h"
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#define LOG_MODULE "EFuse"
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#define LOG_LEVEL LOG_LEVEL_MAIN
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/*---------------------------------------------------------------------------*/
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#define PMU_MC_HW_SLP_TYPE (PMU_BASE + 0x0b0)
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#define PMU_MC_CLK_RES_CTRL (PMU_BASE + 0x0f4)
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#define PMU_CKPHY_FC_CTRL (PMU_BASE + 0x15c)
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#define SYS_BOOT_CNTRL (CIU_BASE + 0x20)
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/*---------------------------------------------------------------------------*/
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#define GEU_FUSE_BLOCK_SIZE (32) /*bytes, 256bits */
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#define GEU_FUSE_BANK0_207_192 (GEU_BASE + 0x0418)
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#define GEU_FUSE_BANK0_31_0 (GEU_BASE + 0x0500)
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#define GEU_BLOCK3_RESERVED_31_0 (GEU_BASE + 0x0490)
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/*#define GEU_BLOCK3_RESERVED_63_32 (GEU_BASE + 0x0494) */
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/*#define GEU_BLOCK3_RESERVED_95_64 (GEU_BASE + 0x0498) */
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/*#define GEU_BLOCK3_RESERVED_127_96 (GEU_BASE + 0x049C) */
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/*#define GEU_BLOCK3_RESERVED_159_128 (GEU_BASE + 0x04A0) */
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#define GEU_BLOCK3_RESERVED_191_160 (GEU_BASE + 0x04A4)
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#define GEU_BLOCK3_RESERVED_223_192 (GEU_BASE + 0x041C)
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#define GEU_BLOCK3_RESERVED_255_224 (GEU_BASE + 0x0420)
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#define GEU_FUSE_VAL_APCFG1 (GEU_BASE + 0x0404)
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#define GEU_FUSE_VAL_APCFG3 (GEU_BASE + 0x040C)
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#define BANK0_EMBED_FLASH_BIT (28)
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/*---------------------------------------------------------------------------*/
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/* craneM A0 and craneG A0 */
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typedef struct bank3_cranem_s {
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unsigned mem_repair_bit[5]; /* bit 0~159*/
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/*160~191*/
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unsigned mem_repair_bit_6 : 8; /* bit 160~167*/
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unsigned psram_edition : 5; /* bit 168~172*/
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unsigned device_version : 2; /* bit 173~174*/
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unsigned y_location : 7; /* bit 175~181*/
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unsigned x_location : 7; /* bit 182~188*/
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#define FUSE_WAFERID_0_BITS (3)
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unsigned waferid_0 : 3; /* bit 189~191*/
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/*192~223*/
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unsigned waferid_1 : 2; /* bit 192~193*/
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unsigned lotid5 : 6; /* bit 194~199*/
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unsigned lotid4 : 6; /* bit 200~205*/
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unsigned lotid3 : 6; /* bit 206~211*/
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unsigned lotid2 : 6; /* bit 212~217*/
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unsigned lotid1 : 6; /* bit 218~223*/
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/*224~255*/
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unsigned lotid0 : 6; /* bit 224~229*/
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unsigned hvtdro : 8; /* bit 230~237*/
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unsigned lvtdro : 8; /* bit 238~245*/
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unsigned svtdro : 8; /* bit 246~253*/
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unsigned cp_good_die : 1; /* bit 254 */
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unsigned fd_good_die : 1; /* bit 255 */
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} bank3_cranem_t;
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/*---------------------------------------------------------------------------*/
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typedef struct bank3_crane_s {
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unsigned mem_repair_bit[5]; /* bit 0~159*/
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/*160~191*/
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unsigned mem_repair_bit_6 : 8; /* bit 160~167*/
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unsigned psram_edition : 3; /* bit 168~170*/
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unsigned gooddie_baddie : 1; /* bit 171 */
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unsigned y_location : 7; /* bit 172~178*/
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unsigned x_location : 7; /* bit 179~185*/
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unsigned waferid : 5; /* bit 186~190*/
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#define FUSE_CHIPVER_0_BITS (1)
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unsigned chipver_0 : 1; /* bit 191 */
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/*192~223*/
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unsigned chipver_1 : 1; /* bit 192 */
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unsigned lotid5 : 7; /* bit 193~199*/
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unsigned lotid4 : 7; /* bit 200~206*/
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unsigned lotid3 : 7; /* bit 207~213*/
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unsigned lotid2 : 7; /* bit 214~220*/
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#define FUSE_LOTID1_0_BITS (3)
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unsigned lotid1_0 : 3; /* bit 221~223*/
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/*224~255*/
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unsigned lotid1_1 : 4; /* bit 224~227*/
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unsigned lotid0 : 7; /* bit 228~234*/
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unsigned lvtdro : 8; /* bit 235~242*/
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unsigned svtdro : 8; /* bit 243~250*/
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unsigned fundryid : 3; /* bit 251~253 */
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unsigned fuse_ver_id : 2; /* bit 254~255 */
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} bank3_crane_t;
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/*---------------------------------------------------------------------------*/
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/* craneL A0*/
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typedef struct bank3_cranel_a0_s {
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unsigned mem_repair_bit[5]; /* bit 0~159*/
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/*160~191*/
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unsigned mem_repair_bit_6 : 8; /* bit 160~167*/
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unsigned psram_edition : 4; /* bit 168~171*//* craneL A0 use bit93 to replace bank3 bit172 for msb of psram type */
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unsigned device_version : 3; /* bit 172~174*/
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unsigned y_location : 7; /* bit 175~181*/
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unsigned x_location : 7; /* bit 182~188*/
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#define CRANEL_A0_FUSE_WAFERID_0_BITS (3)
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unsigned waferid_0 : 3; /* bit 189~191*/
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/*192~223*/
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unsigned waferid_1 : 2; /* bit 192~193*/
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unsigned lotid5 : 6; /* bit 194~199*/
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unsigned lotid4 : 6; /* bit 200~205*/
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unsigned lotid3 : 6; /* bit 206~211*/
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unsigned lotid2 : 6; /* bit 212~217*/
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unsigned lotid1 : 6; /* bit 218~223*/
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/*224~255*/
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unsigned lotid0 : 6; /* bit 224~229*/
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unsigned hvtdro : 8; /* bit 230~237*/
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unsigned lvtdro : 8; /* bit 238~245*/
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unsigned svtdro : 8; /* bit 246~253*/
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unsigned cp_good_die : 1; /* bit 254 */
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unsigned fd_good_die : 1; /* bit 255 */
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} bank3_cranel_a0_t;
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/*---------------------------------------------------------------------------*/
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/* uuid refer to sdk utilities.c Read_Crane_CPU_UID() */
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/* craneLG: no psram_edition, add lotid_6 */
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typedef struct bank3_cranelg_s {
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unsigned mem_repair_bit[5]; /* bit 0~159*/
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/*160~191*/
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unsigned mem_repair_bit_6 : 8; /* bit 160~167*/
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unsigned rsvd_0 : 1; /* bit 168 */
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unsigned y_location : 7; /* bit 169~175*/
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unsigned x_location : 7; /* bit 176~182*/
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unsigned waferid : 5; /* bit 183~187*/
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#define CRANEL_A0_FUSE_LOTID6_0_BITS (4)
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unsigned lotid6_0 : 4; /* bit 188~192*/
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/*192~223*/
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unsigned lotid6_1 : 2; /* bit 192~193*/
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unsigned lotid5 : 6; /* bit 194~199*/
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unsigned lotid4 : 6; /* bit 200~205*/
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unsigned lotid3 : 6; /* bit 206~211*/
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unsigned lotid2 : 6; /* bit 212~217*/
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unsigned lotid1 : 6; /* bit 218~223*/
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/*224~255*/
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unsigned lotid0 : 6; /* bit 224~229*/
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unsigned hvtdro : 8; /* bit 230~237*/
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unsigned lvtdro : 8; /* bit 238~245*/
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unsigned svtdro : 8; /* bit 246~253*/
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unsigned cp_good_die : 1; /* bit 254 */
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unsigned fd_good_die : 1; /* bit 255 */
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} bank3_cranelg_t;
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/*---------------------------------------------------------------------------*/
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/*CIU: SYS_BOOT_CNTRL */
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typedef union {
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struct {
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unsigned debug_en : 1; /* bit 0 */
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unsigned ncsah : 4; /* bit 4:1 */
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unsigned reserved_0 : 1; /* bit 5 */
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unsigned jtag_disable : 1; /* bit 6 */
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unsigned reserved_1 : 5; /* bit 11:7 */
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unsigned uart_port : 1; /* bit 12 */
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unsigned usb_port : 1; /* bit 13 */
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unsigned reserved_2 : 1; /* bit 14 */
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unsigned bootfrom : 1; /* bit 15 */
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unsigned usb_wakeup : 1; /* bit 16 */
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unsigned no_nand_device : 1; /* bit 17 */
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unsigned secure_key_access_disable : 1; /* bit 18 */
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unsigned download_disable : 1; /* bit 19 */
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unsigned sbe : 1; /* bit 20 */
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unsigned sde : 1; /* bit 21 */
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unsigned boot_pltfm_state : 4; /* bit 25:22 */
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unsigned reserved_3 : 6; /* bit 31:26 */
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} s;
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unsigned value;
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} icu_sys_boot_cntrl_t;
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/*---------------------------------------------------------------------------*/
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/*
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* chips：no psram phy, can use auto detect psram type
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* psram driver try windond read, apm read to get psram type and size
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* new chips which support auto_detect, no fuse bits for psram_type, eg: craneLG
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* cr5: fulmar use ddr instead of psram; watch1 z1 and A0 use psram no phy, support auto detect, no need fuse
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*/
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static bool
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_is_chip_support_auto_detect(int *is_fuse_has_psram_type)
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{
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#if AROM_VERSION == AROM_VER_2022_07_28_WATCH1
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/* Watch1 */
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/* LOG_PRINT("psram watch1 %s:%d\n", __FILE__, __LINE__); */
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*is_fuse_has_psram_type = 0;
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return true;
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#elif AROM_VERSION == AROM_VER_2022_11_06_CRANEL_CR5
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if((hw_chip_id() == CHIP_ID_CRANELS) || (hw_chip_id() == CHIP_ID_CRANELR)) {
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/* CraneLS/LR */
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/* LOG_PRINT("psram cranels/lr %s:%d\n", __FILE__, __LINE__); */
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*is_fuse_has_psram_type = 1;
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return true;
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}
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else {
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/* CraneLG/LRH/LB */
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/* LOG_PRINT("psram cranelg/lrh/lb %s:%d\n", __FILE__, __LINE__); */
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*is_fuse_has_psram_type = 0;
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return true;
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}
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#else
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/* Other chips */
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/* LOG_PRINT("psram other %s:%d\n", __FILE__, __LINE__); */
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*is_fuse_has_psram_type = 0;
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return false;
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#endif
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}
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/*---------------------------------------------------------------------------*/
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bool
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is_chip_support_auto_detect(void)
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{
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int is_fuse_has_psram_type = 0;
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return _is_chip_support_auto_detect(&is_fuse_has_psram_type);
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}
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#if ((AROM_VERSION == AROM_VER_2021_10_16_CRANEL_A0) || \
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(AROM_VERSION == AROM_VER_2022_11_06_CRANEL_CR5))
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static void
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_get_psram_version_cranel_ls_lr(uint8_t *psram_flag)
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{
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/*
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* MSB: Bank0 Bit[93]
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* LSB: Bank3 Bit 171~168
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*/
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unsigned int apcfg3 = readl(GEU_FUSE_VAL_APCFG3);
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unsigned int cranel_psram_type_bit4 = (apcfg3 & (1 << 13)) ? 1 : 0;
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*psram_flag = (cranel_psram_type_bit4 << 4) | (*psram_flag & 0x2F);
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}
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#endif
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#if AROM_VERSION != AROM_VER_2021_10_16_CRANEL_A0
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static void
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_get_psram_version(uint8_t *psram_flag)
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{
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bool is_psram_type_auto_detect = false;
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int is_fuse_has_psram_type = 0;
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is_psram_type_auto_detect = _is_chip_support_auto_detect(&is_fuse_has_psram_type);
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if(is_psram_type_auto_detect && (0 == is_fuse_has_psram_type)) {
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/*eg: craneLG, new chip supports auto detect psram type, no fuse bits */
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*psram_flag = 0;
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}
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}
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#endif
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/*
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* craneG, craneM, craneL, craneLS, craneLR, cranew cr5
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* craneGT use this 6bits as DDR type
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*/
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unsigned int
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efuse_get_psram_version(void)
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{
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unsigned value;
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uint8_t psram_flag;
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/* craneg/cranem/cranegt */
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value = readl(GEU_BLOCK3_RESERVED_191_160);
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/* LOG_INFO("fuse read GEU_BLOCK3_RESERVED_191_160, value=0x%x\n", value); */
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/* bit 168~172, 5bits*/
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psram_flag = (value >> 8) & 0x1F;
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#ifdef BOARD_CRANE
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/* cranes Bank0 Bit207 as psram_type_bit5, eg: craneL/LR/LS, cranew CR5, craneGT ddr_type */
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value = readl(GEU_FUSE_BANK0_207_192) & 0xffff;
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value = (value >> 15) & 0x1;
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psram_flag |= (value << 5);
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#endif
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#if AROM_VERSION == AROM_VER_2021_10_16_CRANEL_A0
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/* CraneL */
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/* LOG_PRINT("psram cranel %s:%d\n", __FILE__, __LINE__); */
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_get_psram_version_cranel_ls_lr(&psram_flag);
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#elif AROM_VERSION == AROM_VER_2022_11_06_CRANEL_CR5
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if(CHIP_ID_CRANELS == hw_chip_id() ||
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CHIP_ID_CRANELR == hw_chip_id()) {
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/* CraneLS/LR */
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/* LOG_PRINT("psram cranels/lr %s:%d\n", __FILE__, __LINE__); */
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_get_psram_version_cranel_ls_lr(&psram_flag);
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}
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else {
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/* CraneLG/LRH/LB */
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/* LOG_PRINT("psram cranelg/lrh/lb %s:%d\n", __FILE__, __LINE__); */
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_get_psram_version(&psram_flag);
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}
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#else
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/* Other chips */
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/* LOG_PRINT("psram other %s:%d\n", __FILE__, __LINE__); */
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_get_psram_version(&psram_flag);
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#endif
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return psram_flag;
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}
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/*---------------------------------------------------------------------------*/
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/*
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* eg: craneGT has ddr instead of psram
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* not use efuse_get_psram_version(), Bit 172~168;
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* use auto detect ddr type method to get ddr size, efuse ddr type can be empty.
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* preboot set prop, flasher read prop to get ddr size.
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*/
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unsigned int
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get_ddr_size(void)
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{
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unsigned int ddr_size = DRAM_SIZE_32M;
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const char *prop_str;
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prop_str = asr_property_get("fuse.psram.type"); /*ddr also use it. */
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if(NULL == prop_str) {
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LOG_PRINT("get prop fuse.psram.type failed!\n");
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return ddr_size;
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}
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/*
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* Size <- Key Words in Type
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* 32MB "32M"
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* 64MB "64M"
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*/
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if(strstr(prop_str, "32M")) {
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/*
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* DRAM_AP_32M, DRAM_UniIC_32M
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*/
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ddr_size = DRAM_SIZE_32M;
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} else if(strstr(prop_str, "64M")) {
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/*
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* DRAM_AP_64M, DRAM_UniIC_64M
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*/
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ddr_size = DRAM_SIZE_64M;
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} else {
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LOG_PRINT("Unknow dram device\n");
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}
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return ddr_size;
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}
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/*
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* not use efuse_get_psram_version();
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* craneLR, no phy chip use auto detect psram type method to get psram size, efuse psram type is empty.
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* preboot set prop, flasher read prop to get psram size.
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*/
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unsigned int
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get_psram_size(void)
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{
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unsigned int psram_size = PSRAM_SIZE_8M;
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const char *prop_str;
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if(hw_platform_type() == HW_PLATFORM_TYPE_FPGA) {
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return PSRAM_SIZE_16M;
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}
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prop_str = asr_property_get("fuse.psram.type");
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if(NULL == prop_str) {
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LOG_PRINT("get prop fuse.psram.type failed!\n");
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return psram_size;
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}
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/*
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* Size <- Key Words in Type
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* 32MB "32M", "256Mb"
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* 16MB "16M", "8M8M"
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* 8MB "8M"
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* 4MB "4M"
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*/
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if(strstr(prop_str, "32M") || strstr(prop_str, "256Mb")) {
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/*
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* WB_32M, AP256Mb_1_2V_X16_CS0, AP256Mb_1_2V_X16_CS1,
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* AP256Mb_1_2V_X16_CS0_CS1, WB256Mb_1_8V_X16_CS0,
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* WB256Mb_1_8V_X16_CS1, WB256Mb_1_8V_X16_CS0_CS1
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*/
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psram_size = PSRAM_SIZE_32M;
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} else if(strstr(prop_str, "16M") || strstr(prop_str, "8M8M")) {
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/*
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* AP_16M, WB_16M, AP_8M8M, WB_8M8M, AP_UHS_8M8M, WB_250MHZ_8M8M,
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* AP_250MHZ_8M8M, AP_250MHZ_16M, WB_250MHZ_16M, WB_XCCELA_8M8M,
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* UNIIC_16M
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*
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* "8M8M" must be compared before "8M".
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*/
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psram_size = PSRAM_SIZE_16M;
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} else if(strstr(prop_str, "8M")) {
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/*
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* AP_8M, WB_8M, AP_250MHZ_8M, WB_250MHZ_8M, WB_XCCELA_8M
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*
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* Since the previous branch has already ruled out the case of "8M8M",
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* the "8M" here definitely does not refer to the 8M in "8M8M".
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*/
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psram_size = PSRAM_SIZE_8M;
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} else if(strstr(prop_str, "4M")) {
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/*
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* WB_4M, AP_4M, WB_XCCELA_4M, UNIIC_4M
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*/
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psram_size = PSRAM_SIZE_4M;
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} else {
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LOG_PRINT("Unknow psram device\n");
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}
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return psram_size;
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}
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/*---------------------------------------------------------------------------*/
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/* cranew mcu */
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unsigned
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efuse_cranew_mcu_psram(void)
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{
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unsigned value;
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value = readl(GEU_BLOCK3_RESERVED_31_0);
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/*LOG_INFO("fuse read GEU_BLOCK3_RESERVED_191_160, value=0x%x\n", value); */
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/*bit 11~15, 5bits*/
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uint8_t psram_flag = (value >> 11) & 0x1F;
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return psram_flag;
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Check modem capability by Fuse Bank0 Bit[15]
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* 1: Modem type is zero, no modem capability
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* 0: Modem type is raido, full modem capability
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*/
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bool
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efuse_modem_type_is_radio(void)
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{
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return (readl(GEU_FUSE_BANK0_31_0) & (0x1U << 15)) == 0;
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}
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/*---------------------------------------------------------------------------*/
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/*
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* registers for bank3
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* GEU_BLOCK3_RESERVED_31_0 (GEU_BASE + 0x0490)
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* GEU_BLOCK3_RESERVED_63_32 (GEU_BASE + 0x0494)
|
||
* GEU_BLOCK3_RESERVED_95_64 (GEU_BASE + 0x0498)
|
||
* GEU_BLOCK3_RESERVED_127_96 (GEU_BASE + 0x049C)
|
||
* GEU_BLOCK3_RESERVED_159_128 (GEU_BASE + 0x04A0)
|
||
* GEU_BLOCK3_RESERVED_191_160 (GEU_BASE + 0x04A4)
|
||
* GEU_BLOCK3_RESERVED_223_192 (GEU_BASE + 0x041C)
|
||
* GEU_BLOCK3_RESERVED_255_224 (GEU_BASE + 0x0420)
|
||
|
||
* MEM Repair Bits:168; bit 167:0
|
||
* Manufacturing Parameter0: 88; bit 255:168
|
||
*/
|
||
int
|
||
fuse_read_bank3(void *data)
|
||
{
|
||
unsigned *ptr = (unsigned *)data;
|
||
|
||
for(unsigned i = 0; i < 6; i++) {
|
||
ptr[i] = readl(GEU_BLOCK3_RESERVED_31_0 + 4 * i);
|
||
}
|
||
|
||
ptr[6] = readl(GEU_BLOCK3_RESERVED_223_192);
|
||
ptr[7] = readl(GEU_BLOCK3_RESERVED_255_224);
|
||
|
||
return 0;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
#if ((AROM_VERSION != AROM_VER_2021_10_16_CRANEL_A0) && \
|
||
(AROM_VERSION != AROM_VER_2022_11_06_CRANEL_CR5))
|
||
static void
|
||
fuse_read_lotid_cranem(void)
|
||
{
|
||
unsigned buf[8];
|
||
|
||
memset(buf, 0, GEU_FUSE_BLOCK_SIZE);
|
||
fuse_read_bank3(buf);
|
||
|
||
bank3_cranem_t *ptr = (bank3_cranem_t *)buf;
|
||
unsigned wafer = (ptr->waferid_1 << FUSE_WAFERID_0_BITS) | ptr->waferid_0;
|
||
|
||
LOG_INFO("lotid[0..5]: %d %d %d %d %d %d\n", ptr->lotid0, ptr->lotid1, ptr->lotid2, ptr->lotid3, ptr->lotid4, ptr->lotid5);
|
||
LOG_INFO("X_location: %d, Y_location: %d, Wafer: %d\n", ptr->x_location, ptr->y_location, wafer);
|
||
}
|
||
#endif
|
||
/*---------------------------------------------------------------------------*/
|
||
#if 0
|
||
/* DO not support Crane */
|
||
static void
|
||
fuse_read_lotid_crane(void)
|
||
{
|
||
unsigned buf[8];
|
||
|
||
memset(buf, 0, GEU_FUSE_BLOCK_SIZE);
|
||
fuse_read_bank3(buf);
|
||
|
||
bank3_crane_t *ptr = (bank3_crane_t *)buf;
|
||
unsigned lotid1 = (ptr->lotid1_1 << FUSE_LOTID1_0_BITS) | ptr->lotid1_0;
|
||
|
||
LOG_INFO("lotid[0..5]: %d %d %d %d %d %d\n", ptr->lotid0, lotid1, ptr->lotid2, ptr->lotid3, ptr->lotid4, ptr->lotid5);
|
||
LOG_INFO("X_location: %d, Y_location: %d, Wafer: %d\n", ptr->x_location, ptr->y_location, ptr->waferid);
|
||
}
|
||
#endif
|
||
/*---------------------------------------------------------------------------*/
|
||
#if ((AROM_VERSION == AROM_VER_2021_10_16_CRANEL_A0) || \
|
||
(AROM_VERSION == AROM_VER_2022_11_06_CRANEL_CR5))
|
||
static void
|
||
fuse_read_lotid_cranel_A0(void)
|
||
{
|
||
unsigned buf[8];
|
||
|
||
memset(buf, 0, GEU_FUSE_BLOCK_SIZE);
|
||
fuse_read_bank3(buf);
|
||
|
||
bank3_cranel_a0_t *ptr = (bank3_cranel_a0_t *)buf;
|
||
unsigned wafer = (ptr->waferid_1 << CRANEL_A0_FUSE_WAFERID_0_BITS) | ptr->waferid_0;
|
||
|
||
LOG_INFO("lotid[0..5]: %d %d %d %d %d %d\n", ptr->lotid0, ptr->lotid1, ptr->lotid2, ptr->lotid3, ptr->lotid4, ptr->lotid5);
|
||
LOG_INFO("X_location: %d, Y_location: %d, Wafer: %d\n", ptr->x_location, ptr->y_location, wafer);
|
||
}
|
||
#endif
|
||
/*---------------------------------------------------------------------------*/
|
||
#if AROM_VERSION == AROM_VER_2022_11_06_CRANEL_CR5
|
||
static void
|
||
fuse_read_lotid_cranelg(void)
|
||
{
|
||
unsigned buf[8];
|
||
|
||
memset(buf, 0, GEU_FUSE_BLOCK_SIZE);
|
||
fuse_read_bank3(buf);
|
||
|
||
bank3_cranelg_t *ptr = (bank3_cranelg_t *)buf;
|
||
unsigned lotid6 = (ptr->lotid6_1 << CRANEL_A0_FUSE_LOTID6_0_BITS) | ptr->lotid6_0;
|
||
|
||
LOG_INFO("lotid[0..6]: %d %d %d %d %d %d %d\n", ptr->lotid0, ptr->lotid1, ptr->lotid2, ptr->lotid3, ptr->lotid4, ptr->lotid5, lotid6);
|
||
LOG_INFO("X_location: %d, Y_location: %d, Wafer: %d\n", ptr->x_location, ptr->y_location, ptr->waferid);
|
||
}
|
||
#endif
|
||
/*---------------------------------------------------------------------------*/
|
||
void
|
||
fuse_read_lotid(void)
|
||
{
|
||
/* Do not support Crane */
|
||
#if AROM_VERSION == AROM_VER_2021_10_16_CRANEL_A0
|
||
/* CraneL */
|
||
/* LOG_PRINT("psram cranel %s:%d\n", __FILE__, __LINE__); */
|
||
fuse_read_lotid_cranel_A0();
|
||
#elif AROM_VERSION == AROM_VER_2022_11_06_CRANEL_CR5
|
||
if((hw_chip_id() == CHIP_ID_CRANELS) ||
|
||
(hw_chip_id() == CHIP_ID_CRANELR) ||
|
||
(hw_chip_id() == CHIP_ID_CRANELRH)) {
|
||
/* CraneLS/LR/LRH */
|
||
/* LOG_PRINT("psram cranels/lr/lrh %s:%d\n", __FILE__, __LINE__); */
|
||
fuse_read_lotid_cranel_A0();
|
||
}
|
||
else {
|
||
/* CraneLG/LB */
|
||
/* LOG_PRINT("psram cranelg/lb %s:%d\n", __FILE__, __LINE__); */
|
||
fuse_read_lotid_cranelg();
|
||
}
|
||
#else
|
||
/* Other chips */
|
||
/* LOG_PRINT("psram other %s:%d\n", __FILE__, __LINE__); */
|
||
fuse_read_lotid_cranem();
|
||
#endif
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
/* bootrom operation mode, block[91:90], apconfig[75:74], APGFG3[11:10], map to CIU: SYS_BOOT_CNTRL[20] */
|
||
int
|
||
fuse_trust_boot_enabled(void)
|
||
{
|
||
icu_sys_boot_cntrl_t sys_boot_ctrl;
|
||
|
||
sys_boot_ctrl.value = readl(SYS_BOOT_CNTRL);
|
||
|
||
/*LOG_INFO("fuse: sbe = %d, sys_boot_ctrl=0x%x\n", sys_boot_ctrl.s.sbe, (unsigned int)sys_boot_ctrl.value); */
|
||
return sys_boot_ctrl.s.sbe != 0;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|