102 lines
1.7 KiB
C
102 lines
1.7 KiB
C
#ifndef _QSPI_HOST_H
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#define _QSPI_HOST_H
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#include "common.h"
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#include "qspi_flash.h"
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#define QSPI_RX_BUFF_MAX 32
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#define QSPI_TX_BUFF_MAX 32
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#define QSPI_TX_BUFF_POP_MIN 16
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#define QSPI_AHB_BUFF_MAX_SIZE (256*3)
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#define QSPI_DMA_TX_CHANNEL 28
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#define ENABLE_QSPI_INT
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#define ENABLE_QSPI_DMA
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struct spi_flash_cmd;
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enum {
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QSPI_LUT_NOTSET = -1,
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QSPI_LUT_SEQID0 = 0,
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QSPI_LUT_SEQID1,
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QSPI_LUT_SEQID2,
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QSPI_LUT_SEQID3,
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QSPI_LUT_SEQID4,
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QSPI_LUT_SEQID5,
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QSPI_LUT_SEQID6,
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QSPI_LUT_SEQID7,
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QSPI_LUT_SEQID8,
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QSPI_LUT_SEQID9,
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QSPI_LUT_SEQID10,
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QSPI_LUT_SEQID11,
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QSPI_LUT_SEQID12,
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QSPI_LUT_SEQID13,
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QSPI_LUT_SEQID14,
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QSPI_LUT_SEQID15
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};
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enum {
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QSPI_NORMAL_MODE = 0,
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QSPI_DISABLE_MODE,
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QSPI_STOP_MODE
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};
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enum {
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QSPI_FUNC_CLK_26MHZ = 0,
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QSPI_FUNC_CLK_52MHZ,
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QSPI_FUNC_CLK_78MHZ,
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QSPI_FUNC_CLK_104MHZ,
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QSPI_FUNC_CLK_156MHZ,
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QSPI_FUNC_CLK_208MHZ,
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QSPI_FUNC_CLK_312MHZ,
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QSPI_FUNC_CLK_416MHZ
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};
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enum {
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QSPI_CS_A1 = 0,
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QSPI_CS_A2,
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QSPI_CS_B1,
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QSPI_CS_B2,
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QSPI_CS_MAX
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};
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enum {
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QSPI_CPU_XFER = 0,
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QSPI_DMA_XFER
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};
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enum QSPI_PAD_E {
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QSPI_PAD_1X = 0x0,
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QSPI_PAD_2X = 0x1,
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QSPI_PAD_4X = 0x2,
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QSPI_PAD_RSVD = 0x3
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};
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struct qspi_host
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{
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struct spi_flash_cmd *cmd;
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int bytes_left;
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volatile int complete;
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int wmrk;
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int cs_addr[QSPI_CS_MAX];
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int use_intr;
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int en_tx_dma;
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int use_dma;
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int use_xip;
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int xip_read;
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int bus_clk;
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int lut_map;
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};
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int qspi_enable_xip(struct spi_flash_chip *chip,
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struct spi_flash_cmd_cfg *cmd_cfg);
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int qspi_preinit_lookup_tbl(struct spi_flash_chip *chip);
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struct qspi_host * qspi_host_init(int cs, int mhz, int use_xip);
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int qspi_start_cmd(struct spi_flash_chip *chip, struct spi_flash_cmd *cmd);
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#endif
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