458 lines
16 KiB
C
458 lines
16 KiB
C
/******************************************************************************
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**
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** COPYRIGHT (C) 2001, 2002 Intel Corporation.
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**
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** This software as well as the software described in it is furnished under
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** license and may only be used or copied in accordance with the terms of the
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** license. The information in this file is furnished for informational use
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** only, is subject to change without notice, and should not be construed as
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** a commitment by Intel Corporation. Intel Corporation assumes no
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** responsibility or liability for any errors or inaccuracies that may appear
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** in this document or any software that may be provided in association with
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** this document.
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** Except as permitted by such license, no part of this document may be
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** reproduced, stored in a retrieval system, or transmitted in any form or by
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** any means without the express written consent of Intel Corporation.
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**
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** FILENAME: xllp_dmac.h
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**
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** PURPOSE: contains all DMA Controller specific macros, typedefs, and prototypes.
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** Declares no storage.
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**
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**
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******************************************************************************/
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/******************************************************************************
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*
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* (C)Copyright 2005 - 2011 Marvell. All Rights Reserved.
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*
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* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
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* The copyright notice above does not evidence any actual or intended
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* publication of such source code.
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* This Module contains Proprietary Information of Marvell and should be
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* treated as Confidential.
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* The information in this file is provided for the exclusive use of the
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* licensees of Marvell.
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* Such users have the right to use, modify, and incorporate this code into
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* products for purposes authorized by the license agreement provided they
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* include this notice and the associated copyright notice with any such
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* product.
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* The information in this file is provided "AS IS" without warranty.
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******************************************************************************
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**
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** FILENAME: xllp_dmac.c
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**
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** PURPOSE: contains all primitive functions for Bulverde DMA Controller register
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** access and control
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**
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******************************************************************************/
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#ifndef __DMAC_H__
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#define __DMAC_H__
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#include "xllp_defs.h"
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#include "dma.h"
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#define MAX_DMA_CHANNELS 32
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#define DMA_STATUS_INTERRUPTS_MASK 0x01000217
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/**
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* DCSR Register
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**/
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#define XLLP_DMAC_DCSR_BUS_ERR_INTR (1U<<0)
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#define XLLP_DMAC_DCSR_START_INTR (1U<<1)
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#define XLLP_DMAC_DCSR_END_INTR (1U<<2)
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#define XLLP_DMAC_DCSR_STOP_INTR (1U<<3)
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#define XLLP_DMAC_DCSR_RAS_INTR (1U<<4)
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#define XLLP_DMAC_DCSR_REQ_PEND (1U<<8)
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#define XLLP_DMAC_DCSR_EOR_INTR (1U<<9)
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#define XLLP_DMAC_DCSR_CMP_ST (1U<<10)
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#define XLLP_DMAC_DCSR_MASK_RUN (1U<<22)
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#define XLLP_DMAC_DCSR_RAS_EN (1U<<23)
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#define XLLP_DMAC_DCSR_CLR_CMP_ST (1U<<24)
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#define XLLP_DMAC_DCSR_SET_CMP_ST (1U<<25)
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#define XLLP_DMAC_DCSR_EOR_STOP_EN (1U<<26)
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#define XLLP_DMAC_DCSR_EOR_JMP_ENT (1U<<27)
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#define XLLP_DMAC_DCSR_EOR_IRQ_EN (1U<<28)
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#define XLLP_DMAC_DCSR_STOP_IRQ_EN (1U<<29)
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#define XLLP_DMAC_DCSR_NO_DESC_FETCH (1U<<30)
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#define XLLP_DMAC_DCSR_RUN (1U<<31)
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#define XLLP_DMAC_DCSR_WRITABLES_MSK 0xFFC00617
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/**
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* DCMD Register
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**/
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#define XLLP_DMAC_DCMD_LEN (1U<<0)
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#define XLLP_DMAC_DCMD_WIDTH (1U<<14)
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#define XLLP_DMAC_DCMD_SIZE (1U<<16)
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#define XLLP_DMAC_DCMD_FLY_BY_T (1U<<19)
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#define XLLP_DMAC_DCMD_FLY_BY_S (1U<<20)
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#define XLLP_DMAC_DCMD_END_IRQ_EN (1U<<21)
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#define XLLP_DMAC_DCMD_START_IRQ_EN (1U<<22)
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#define XLLP_DMAC_DCMD_ADDR_MODE (1U<<23)
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#define XLLP_DMAC_DCMD_CMP_EN (1U<<25)
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#define XLLP_DMAC_DCMD_FLOW_TRG (1U<<28)
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#define XLLP_DMAC_DCMD_FLOW_SRC (1U<<29)
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#define XLLP_DMAC_DCMD_INC_TRG_ADDR (1U<<30)
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#define XLLP_DMAC_DCMD_INC_SRC_ADDR (1U<<31)
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#define XLLP_DMAC_DDADR_RESERVED_MASK 0xFFFFFFF0
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#define XLLP_DMAC_DRCMR_ENABLE 0x80
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#define XLLP_DMAC_DRCMR_DISABLE 0x00
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/**
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* DMAC DDADRx bit fields
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**/
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#define XLLP_DMAC_DDADR_STOP (1<<0)
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#define XLLP_DMAC_DDADR_BREN (1<<1)
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/**
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* Used in DMA handler definition
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**/
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#define XLLP_DMAC_CHANNEL_NUM 32
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#define XLLP_DMAC_DRCMR1_NUM 64
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#define XLLP_DMAC_DRCMR2_NUM 36
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/**
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* Some error codes
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**/
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#define XLLP_ERR_BAD_CHANNEL -1
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#define XLLP_ERR_CHANNEL_NOT_ALLOCATED -2
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#define XLLP_ERR_NO_HANDLER -3
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#define XLLP_ERR_MEM_ALLOC -4
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//#define XLLP_DMAC_CHANNEL_INVALID -5
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#define XLLP_DMAC_CHANNEL_INVALID 99
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/**
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* Max length that can be transferred by a single DMA descriptor
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**/
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#define XLLP_DCMD_LEN_MASK 0x1FFFU
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#define XLLP_DMAC_ALIGN_MASK 0xFFFFFFF0U
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#define XLLP_ALL_INTERRUPTS (XLLP_DMAC_DCSR_BUS_ERR_INTR|\
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XLLP_DMAC_DCSR_START_INTR |\
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XLLP_DMAC_DCSR_END_INTR |\
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XLLP_DMAC_DCSR_STOP_INTR |\
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XLLP_DMAC_DCSR_EOR_INTR)
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/**
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* Mask of all writable bits in DCSR; others must be written as 0
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**/
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#define XLLP_DCSR_WRITABLES_MSK (XLLP_DMAC_DCSR_BUS_ERR_INTR |\
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XLLP_DMAC_DCSR_START_INTR |\
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XLLP_DMAC_DCSR_END_INTR |\
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XLLP_DMAC_DCSR_RAS_INTR |\
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XLLP_DMAC_DCSR_EOR_INTR |\
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XLLP_DMAC_DCSR_CMP_ST |\
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XLLP_DMAC_DCSR_MASK_RUN |\
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XLLP_DMAC_DCSR_STOP_IRQ_EN |\
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XLLP_DMAC_DCSR_NO_DESC_FETCH|\
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XLLP_DMAC_DCSR_RUN )
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/**
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* DMA Descriptor
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**/
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typedef struct
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{
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XLLP_VUINT32_T DDADR; // descriptor address reg
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XLLP_VUINT32_T DSADR; // source address register
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XLLP_VUINT32_T DTADR; // target address register
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XLLP_VUINT32_T DCMD; // command address register
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}XLLP_DMAC_DESCRIPTOR_T, *P_XLLP_DMAC_DESCRIPTOR_T;
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/**
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* DMAC Register Definitions
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**/
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typedef struct
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{
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XLLP_VUINT32_T DCSR[XLLP_DMAC_CHANNEL_NUM]; /* DMA Control/Status Registers 0-31 */
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XLLP_VUINT32_T RESERVED0[0x8]; /* RESERVED0 */
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XLLP_VUINT32_T DALGN; /* DMA Alignment Register 31 */
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XLLP_VUINT32_T DPCSR; /* DMA Programmed IO control status reg */
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XLLP_VUINT32_T RESERVED1[0xE]; /* RESERVED0 */
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XLLP_VUINT32_T DRQSR0; /* DMA DREQ(0) Status Register */
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XLLP_VUINT32_T DRQSR1; /* DMA DREQ(1) Status Register */
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XLLP_VUINT32_T DRQSR2; /* DMA DREQ(2) Status Register */
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XLLP_VUINT32_T RESERVED2[0x1]; /* RESERVED1 */
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XLLP_VUINT32_T DINT; /* DMA Interrupt Register */
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XLLP_VUINT32_T RESERVED3[0x3]; /* RESERVED2 */
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XLLP_VUINT32_T DRCMR1[XLLP_DMAC_DRCMR1_NUM];/* Request to Channel Map for DREQ 0-63 */
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XLLP_DMAC_DESCRIPTOR_T DDG[XLLP_DMAC_CHANNEL_NUM]; /* DMA Desc Group for channel 0-31 */
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XLLP_VUINT32_T RESERVED4[0x340]; /* RESERVED3 */
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XLLP_VUINT32_T DRCMR2[XLLP_DMAC_DRCMR2_NUM];/* Request to Channel Map 64-99 */
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} XLLP_DMAC_T, *P_XLLP_DMAC_T;
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/**
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* DMAC peripheral device width
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**/
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typedef enum
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{
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XLLP_DMAC_WIDTH_0 = 0,
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XLLP_DMAC_WIDTH_8,
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XLLP_DMAC_WIDTH_16,
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XLLP_DMAC_WIDTH_32
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}XLLP_DMAC_DEVICE_WIDTH_T;
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/**
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* DMAC status
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**/
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typedef enum
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{
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XLLP_NO_ERROR = 0,
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XLLP_NO_DMA_CHANNEL_AVAILABLE
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}XLLP_DMA_STATUS_T;
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//}XLLP_STATUS_T;
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/**
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* DMAC peripheral burst size
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**/
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typedef enum
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{
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XLLP_DMAC_RESERVED_SIZE = 0,
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XLLP_DMAC_BURSTSIZE_8,
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XLLP_DMAC_BURSTSIZE_16,
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XLLP_DMAC_BURSTSIZE_32
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}XLLP_DMAC_DEVICE_BURSTSIZE_T;
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/**
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* DMAC channels
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**/
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typedef enum
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{
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XLLP_DMAC_CHANNEL_0 = 0,
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XLLP_DMAC_CHANNEL_1,
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XLLP_DMAC_CHANNEL_2,
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XLLP_DMAC_CHANNEL_3,
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XLLP_DMAC_CHANNEL_4,
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XLLP_DMAC_CHANNEL_5,
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XLLP_DMAC_CHANNEL_6,
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XLLP_DMAC_CHANNEL_7,
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XLLP_DMAC_CHANNEL_8,
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XLLP_DMAC_CHANNEL_9,
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XLLP_DMAC_CHANNEL_10,
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XLLP_DMAC_CHANNEL_11,
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XLLP_DMAC_CHANNEL_12,
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XLLP_DMAC_CHANNEL_13,
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XLLP_DMAC_CHANNEL_14,
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XLLP_DMAC_CHANNEL_15,
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XLLP_DMAC_CHANNEL_16,
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XLLP_DMAC_CHANNEL_17,
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XLLP_DMAC_CHANNEL_18,
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XLLP_DMAC_CHANNEL_19,
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XLLP_DMAC_CHANNEL_20,
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XLLP_DMAC_CHANNEL_21,
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XLLP_DMAC_CHANNEL_22,
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XLLP_DMAC_CHANNEL_23,
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XLLP_DMAC_CHANNEL_24,
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XLLP_DMAC_CHANNEL_25,
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XLLP_DMAC_CHANNEL_26,
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XLLP_DMAC_CHANNEL_27,
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XLLP_DMAC_CHANNEL_28,
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XLLP_DMAC_CHANNEL_29,
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XLLP_DMAC_CHANNEL_30,
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XLLP_DMAC_CHANNEL_31
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}XLLP_DMAC_CHANNEL_T, *P_XLLP_DMAC_CHANNEL_T;
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#define MEM2MEM_CHANNEL XLLP_DMAC_CHANNEL_20
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#define WTM_CMD_CHANNEL XLLP_DMAC_CHANNEL_0
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#define WTM_RX_CHANNEL XLLP_DMAC_CHANNEL_1
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#define WTM_TX_CHANNEL XLLP_DMAC_CHANNEL_2
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#define USB_RX_CHANNEL XLLP_DMAC_CHANNEL_4
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#define USB_TX_CHANNEL XLLP_DMAC_CHANNEL_5
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#define SSP_TX_CHANNEL XLLP_DMAC_CHANNEL_6 //map GSSP Tx to channel 0
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#define SSP_RX_CHANNEL XLLP_DMAC_CHANNEL_7 //map GSSP Rx to channel 1
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#define UART1_TX_CHANNEL XLLP_DMAC_CHANNEL_0
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#define UART1_RX_CHANNEL XLLP_DMAC_CHANNEL_1
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#define UART2_TX_CHANNEL XLLP_DMAC_CHANNEL_8
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#define UART2_RX_CHANNEL XLLP_DMAC_CHANNEL_9
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#define UART3_TX_CHANNEL XLLP_DMAC_CHANNEL_10
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#define UART3_RX_CHANNEL XLLP_DMAC_CHANNEL_11
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#define UART4_TX_CHANNEL XLLP_DMAC_CHANNEL_12
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#define UART4_RX_CHANNEL XLLP_DMAC_CHANNEL_13
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#define BTUART_TX_CHANNEL UART3_TX_CHANNEL
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#define BTUART_RX_CHANNEL UART3_RX_CHANNEL
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/**
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* DMAC Interrupts
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**/
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typedef enum
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{
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XLLP_DMAC_BUS_ERR_INT = 0,
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XLLP_DMAC_START_INT,
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XLLP_DMAC_END_INT,
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XLLP_DMAC_STOP_INT,
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XLLP_DMAC_EOR_INT = 9
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}XLLP_DMAC_INTERRUPT_T;
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/**
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* DMAC Transfer Type
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**/
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typedef enum
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{
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XLLP_DMAC_TRANSFER_MEM_TO_MEM = 0,
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XLLP_DMAC_TRANSFER_IO_TO_MEM,
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XLLP_DMAC_TRANSFER_MEM_TO_IO
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}XLLP_DMAC_TRANSFER_TYPE_T;
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/**
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* DMAC Transfer Mode
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**/
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typedef enum
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{
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XLLP_DMAC_DESCRIPTOR_MODE = 0,
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XLLP_DMAC_NO_DESCRIPTOR_MODE
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}XLLP_DMAC_TRANSFER_MODE_T;
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/**
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* DMAC Descriptor Branching Mode
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**/
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typedef enum
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{
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XLLP_DMAC_DISABLE_DESC_BRANCH = 0,
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XLLP_DMAC_ENABLE_DESC_BRANCH
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}XLLP_DMAC_DESC_BRANCH_T;
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/**
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* DMAC Descriptor Enable
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**/
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typedef enum
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{
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XLLP_DMAC_DESC_RUN_CHANNEL = 0,
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XLLP_DMAC_DESC_STOP_CHANNEL
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}XLLP_DMAC_DESC_ENABLE_T;
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/**
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* DMA Command - old format
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**/
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typedef struct
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{
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XLLP_INT16_T aLen; // Length of transfer in bytes. Max 0x1FFF
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XLLP_UINT8_T aWidth; // Width of on-chip peripheral
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XLLP_UINT8_T aSize; // Max. burst size of each data transferred
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XLLP_UINT8_T aEndian; // Device endianness. 0=Little, 1=Big endian
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XLLP_UINT8_T aFlyByT; // Fly-By target bit
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XLLP_UINT8_T aFlyByS; // Fly-By source bit
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XLLP_UINT8_T aEndIrqEn; // End Interrupt Enable. When set,
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XLLP_UINT8_T aStartIrqEn; // Start Int. enable. When set, generate
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XLLP_UINT8_T aAddrMode; // Addressing mode for descriptor comparison
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XLLP_UINT8_T aCmpEn; // Descriptor compare enable bit
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XLLP_UINT8_T aFlowTrg; // Flow control of the target.
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XLLP_UINT8_T aFlowSrc; // Flow control of the source
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XLLP_UINT8_T aIncTrgAddr; // Target address increment setting
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XLLP_UINT8_T aIncSrcAddr; // Source address increment setting
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}XLLP_DMAC_COMMAND_T, *P_XLLP_DMAC_COMMAND_T;
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/**
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* DMA CMDx register bit layout
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**/
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struct DMA_CMD_BITS
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{
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unsigned int Length :13; //Bits [12:0]: Length of transfer in Bytes
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unsigned int Reserved4 :1; //Bit 13: reserved
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unsigned int Width :2; //Bits [15:14]: Width of onchip peripheral - 0=reserved, 1=1B, 2=2B, 3=4B
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unsigned int MaxBurstSize :2; //Bits [17:16]: Max Burst Size - 0=reserved, 1=8B, 2=16B, 3=32B
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unsigned int Reserved3 :3; //Bits [20:18]: reserved
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unsigned int EndIRQEn :1; //Bit 21: end interrupt enable
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unsigned int StartIRQEn :1; //Bit 22: start interrupt enable
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unsigned int AddrMode :1; //Bit 23: Addressing mode for descriptor compare - 0=target has addr/1=target has data
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unsigned int Reserved2 :1; //Bit 24: reserved
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unsigned int CmpEn :1; //Bit 25: Compare Enable - descriptor branching compare enable
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unsigned int Reserved1 :2; //Bits [27:26]: reserved
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unsigned int FlowTrg :1; //Bit 28: Target flow control - 1=wait for request signal
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unsigned int FlowSrc :1; //Bit 29: Source flow control - 1=wait for request signal
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unsigned int IncTrgAddr :1; //Bit 30: Target increment - 0=no increment, 1=increment
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unsigned int IncSrcAddr :1; //Bit 31: Source increment - 0=no increment, 1=increment
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};
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typedef union
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{
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unsigned int value;
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struct DMA_CMD_BITS bits;
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} DMA_CMDx_T, *P_DMA_CMDx_T;
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/**
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* DMAC Channel Status
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**/
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typedef enum
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{
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XLLP_DMAC_STATUS_BUSERRINTR = 0, // Bus error causing int.
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XLLP_DMAC_STATUS_STARTINTR, // Successful Descriptor fetch int.
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XLLP_DMAC_STATUS_ENDINTR, // Successful completion int.
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XLLP_DMAC_STATUS_STOPINTR, // Channel state, 0=Running, 1=Stop
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XLLP_DMAC_STATUS_REQPEND = 8, // Channel Request pending state.
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// 1=Channel has pending req, 0=No Req
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XLLP_DMAC_STATUS_EORINT, // Indicates status of peripheral Rx data
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XLLP_DMAC_STATUS_CMPST // Descriptor compare status
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}XLLP_DMAC_CHANNEL_STATUS_T, *P_XLLP_DMAC_CHANNEL_STATUS_T;
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/**
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* DMAC External Request Pins
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**/
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typedef enum
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{
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XLLP_DMAC_EXTERNAL_PIN_0 = 0,
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XLLP_DMAC_EXTERNAL_PIN_1
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}XLLP_DMAC_EXT_PIN_T;
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/**
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* DMAC Data Alignment
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**/
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typedef enum
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{
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XLLP_DMAC_ALIGNMENT_OFF = 0,
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XLLP_DMAC_ALIGNMENT_ON
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}XLLP_DMAC_ALIGNMENT_T;
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/**
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* DMAC Channel Allocation Priority
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**/
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typedef enum
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{
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XLLP_DMAC_CHANNEL_PRIORITY_HIGH = 0,
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XLLP_DMAC_CHANNEL_PRIORITY_MEDIUM,
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XLLP_DMAC_CHANNEL_PRIORITY_LOW,
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XLLP_DMAC_CHANNEL_PRIORITY_LOWEST
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}XLLP_DMAC_CHANNEL_PRIORITY_T;
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#define GlobalDmaBufferSize 1800
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char *GlobalDmaDescAlloc(int RequestedSize);
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/**
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* XLLP DMA Primitive Functions
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**/
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P_XLLP_DMAC_T XLLP_Return_PDmacHandle(void);
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void alignChannel(unsigned int channel, unsigned int user_align);
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void configDescriptor(P_XLLP_DMAC_DESCRIPTOR_T ,P_XLLP_DMAC_DESCRIPTOR_T, unsigned int, \
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unsigned int, P_DMA_CMDx_T, unsigned int, unsigned int);
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void loadDescriptor (P_XLLP_DMAC_DESCRIPTOR_T pDesc, XLLP_DMAC_CHANNEL_T aChannel);
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void XllpDmacMapDeviceToChannel(DMAC_DEVICE_T aDeviceDrcmr,XLLP_DMAC_CHANNEL_T aChannel);
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void XllpDmacUnMapDeviceToChannel(DMAC_DEVICE_T aDeviceDrcmr, XLLP_DMAC_CHANNEL_T aChannel);
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void XllpDmacNoDescriptorFetch( XLLP_DMAC_CHANNEL_T aChannel );
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void XllpDmacDescriptorFetch( XLLP_DMAC_CHANNEL_T aChannel );
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void XllpDmacStartTransfer( XLLP_DMAC_CHANNEL_T aChannel );
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void XllpDmacStopTransfer( XLLP_DMAC_CHANNEL_T aChannel );
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void XllpDmacEnableStopIrqInterrupt( XLLP_DMAC_CHANNEL_T aChannel );
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void XllpDmacDisableStopIrqInterrupt( XLLP_DMAC_CHANNEL_T aChannel );
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void XllpDmacDisableEORInterrupt( XLLP_DMAC_CHANNEL_T aChannel );
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void XllpDmacEnableEORInterrupt( XLLP_DMAC_CHANNEL_T aChannel );
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void XllpDmacClearDmaInterrupt( XLLP_DMAC_CHANNEL_T aChannel );
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unsigned int readDmaStatusRegister(XLLP_DMAC_CHANNEL_T aChannel);
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void loadNonDescriptor (unsigned int Source, unsigned int Target, P_DMA_CMDx_T pCMD, XLLP_DMAC_CHANNEL_T aChannel);
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#endif //__DMAC_H__
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