215 lines
6.2 KiB
C
215 lines
6.2 KiB
C
/*================================================================
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Copyright (c) 2021, Quectel Wireless Solutions Co., Ltd. All rights reserved.
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Quectel Wireless Solutions Proprietary and Confidential.
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=================================================================*/
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/**
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******************************************************************************
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* @file example_eint.c
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* @author Juson.zhang
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* @version V1.0.0
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* @date 2019/01/02
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* @brief This file tests GPIO eint APIs
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******************************************************************************
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*/
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#include <stdio.h>
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#include "ql_gpio.h"
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#include "ql_rtos.h"
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#include "ql_application.h"
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#include "ql_power.h"
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#define test_log(fmt, args...) printf(fmt, ##args)
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#define K1_DN_FLAG (0x01)
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#define K1_UP_FLAG (0x02)
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#define K2_DN_FLAG (0x04)
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#define K2_UP_FLAG (0x08)
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#define PTT_DN_FLAG (0x10)
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#define PTT_UP_FLAG (0x20)
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#define UP_DN_FLAG (0x40)
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#define UP_UP_FLAG (0x80)
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#define DN_DN_FLAG (0x100)
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#define DN_UP_FLAG (0x200)
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#define ANY_KEY_FLAG (0x3FF)
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static int g_test01_cnt = 0;
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static int g_test02_cnt = 0;
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static int g_test03_cnt = 0;
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static int g_test04_cnt = 0;
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static int g_test05_cnt = 0;
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static ql_flag_t key_flag;
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static void __gpio_irq_handler_test01(void)
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{
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PIN_LEVEL_E value;
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g_test01_cnt++;
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ql_gpio_get_level(GPIO_PIN_NO_5, &value);
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test_log("get gpio[%d] level%d \r\n", GPIO_PIN_NO_5, value);
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if(value == PIN_LEVEL_HIGH)
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{
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ql_rtos_flag_release(key_flag, K1_DN_FLAG, QL_FLAG_OR);
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}
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else
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{
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ql_rtos_flag_release(key_flag, K1_UP_FLAG, QL_FLAG_OR);
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}
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ql_eint_enable(GPIO_PIN_NO_5, PIN_BOTH_EDGE); //is needed to active isr
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//ql_eint_enable_wakeup(GPIO_PIN_NO_5, PIN_BOTH_EDGE);
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}
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static void __gpio_irq_handler_test02(void)
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{
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PIN_LEVEL_E value;
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g_test02_cnt++;
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ql_gpio_get_level(GPIO_PIN_NO_121, &value);
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test_log("get gpio[%d] level%d \r\n", GPIO_PIN_NO_121, value);
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if(value == PIN_LEVEL_HIGH)
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{
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ql_rtos_flag_release(key_flag, K2_DN_FLAG, QL_FLAG_OR);
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}
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else
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{
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ql_rtos_flag_release(key_flag, K2_UP_FLAG, QL_FLAG_OR);
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}
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//ql_eint_enable(GPIO_PIN_NO_121, PIN_BOTH_EDGE); //is needed to active isr
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ql_eint_enable_wakeup(GPIO_PIN_NO_121, PIN_BOTH_EDGE);
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}
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static void __gpio_irq_handler_test03(void)
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{
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PIN_LEVEL_E value;
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g_test03_cnt++;
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ql_gpio_get_level(GPIO_PIN_NO_11, &value);
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test_log("get gpio[%d] level%d \r\n", GPIO_PIN_NO_11, value);
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if(value == PIN_LEVEL_HIGH)
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{
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ql_rtos_flag_release(key_flag, PTT_DN_FLAG, QL_FLAG_OR);
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}
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else
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{
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ql_rtos_flag_release(key_flag, PTT_UP_FLAG, QL_FLAG_OR);
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}
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ql_eint_enable(GPIO_PIN_NO_11, PIN_BOTH_EDGE); //is needed to active isr
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}
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static void __gpio_irq_handler_test04(void)
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{
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PIN_LEVEL_E value;
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g_test04_cnt++;
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ql_gpio_get_level(GPIO_PIN_NO_3, &value);
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test_log("get gpio[%d] level%d \r\n", GPIO_PIN_NO_3, value);
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if(value == PIN_LEVEL_HIGH)
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{
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ql_rtos_flag_release(key_flag, UP_DN_FLAG, QL_FLAG_OR);
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}
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else
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{
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ql_rtos_flag_release(key_flag, UP_UP_FLAG, QL_FLAG_OR);
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}
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ql_eint_enable(GPIO_PIN_NO_3, PIN_BOTH_EDGE); //is needed to active isr
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}
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static void __gpio_irq_handler_test05(void)
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{
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PIN_LEVEL_E value;
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g_test05_cnt++;
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ql_gpio_get_level(GPIO_PIN_NO_4, &value);
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test_log("get gpio[%d] level%d \r\n", GPIO_PIN_NO_4, value);
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if(value == PIN_LEVEL_HIGH)
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{
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ql_rtos_flag_release(key_flag, DN_DN_FLAG, QL_FLAG_OR);
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}
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else
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{
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ql_rtos_flag_release(key_flag, DN_UP_FLAG, QL_FLAG_OR);
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}
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ql_eint_enable(GPIO_PIN_NO_4, PIN_BOTH_EDGE); //is needed to active isr
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}
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static void quec_gpio_task(void* argv)
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{
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ql_gpio_init(GPIO_PIN_NO_36,PIN_DIRECTION_OUT,PIN_PULL_PD,PIN_LEVEL_HIGH);
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unsigned int cnt=0;
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ql_rtos_task_sleep_ms(10000);
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while(1)
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{
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ql_gpio_set_level(GPIO_PIN_NO_36,PIN_LEVEL_LOW);
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cnt++;
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printf("\r\ngpio[36]------cnt %d\r\n",cnt);
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ql_rtos_task_sleep_ms(1000);
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ql_gpio_set_level(GPIO_PIN_NO_36,PIN_LEVEL_HIGH);
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cnt++;
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printf("\r\ngpio[36]------cnt %d\r\n",cnt);
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ql_rtos_task_sleep_ms(1000);
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}
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}
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static void quec_eint_test(void * argv)
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{
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int ret = -1;
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int j = 0;
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unsigned int event = 0;
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ql_rtos_flag_create(&key_flag);
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ql_autosleep_enable(QL_ALLOW_SLEEP);
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ret = ql_eint_register(GPIO_PIN_NO_5, PIN_BOTH_EDGE, PIN_PULL_PU, __gpio_irq_handler_test01, NULL);
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// ret = ql_eint_register(GPIO_PIN_NO_5, PIN_BOTH_EDGE, PIN_PULL_PU, __gpio_irq_handler_test01, NULL);
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if (ret) {
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test_log("eint register failed, ret = %d\n", ret);
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return;
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}
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ql_eint_enable(GPIO_PIN_NO_5, PIN_BOTH_EDGE);
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//ql_eint_enable_wakeup(GPIO_PIN_NO_5, PIN_BOTH_EDGE);
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ret = ql_eint_register(GPIO_PIN_NO_121, PIN_BOTH_EDGE, PIN_PULL_PU,NULL, __gpio_irq_handler_test02);
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// ret = ql_eint_register(GPIO_PIN_NO_121, PIN_BOTH_EDGE, PIN_PULL_PU, __gpio_irq_handler_test02, NULL);
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if (ret) {
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test_log("eint register failed, ret = %d\n", ret);
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return;
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}
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ql_eint_enable_wakeup(GPIO_PIN_NO_121, PIN_BOTH_EDGE);
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// ql_eint_enable(GPIO_PIN_NO_121, PIN_BOTH_EDGE);
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ret = ql_eint_register(GPIO_PIN_NO_11, PIN_BOTH_EDGE, PIN_PULL_PU, __gpio_irq_handler_test03, NULL);
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if (ret) {
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test_log("eint register failed, ret = %d\n", ret);
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return;
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}
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ql_eint_enable(GPIO_PIN_NO_11, PIN_BOTH_EDGE);
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ret = ql_eint_register(GPIO_PIN_NO_3, PIN_BOTH_EDGE, PIN_PULL_PU, __gpio_irq_handler_test04, NULL);
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if (ret) {
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test_log("eint register failed, ret = %d\n", ret);
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return;
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}
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ql_eint_enable(GPIO_PIN_NO_3, PIN_BOTH_EDGE);
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ret = ql_eint_register(GPIO_PIN_NO_4, PIN_BOTH_EDGE, PIN_PULL_PU, __gpio_irq_handler_test05, NULL);
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if (ret) {
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test_log("eint register failed, ret = %d\n", ret);
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return;
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}
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ql_eint_enable(GPIO_PIN_NO_4, PIN_BOTH_EDGE);
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while(1) {
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ql_rtos_flag_wait(key_flag, ANY_KEY_FLAG, QL_FLAG_OR_CLEAR, &event, QL_WAIT_FOREVER);
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j++;
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test_log("id:%d, event:0x%X, test01_cnt=%d, test02_cnt=%d, test03_cnt=%d, test04_cnt=%d, test05_cnt=%d\r\n", j, event, g_test01_cnt, g_test02_cnt, g_test03_cnt, g_test04_cnt, g_test05_cnt);
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// ql_rtos_task_sleep_s(3);
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}
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}
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//application_init(quec_eint_test, "quec_eint_test", 2, 0);
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//application_init(quec_gpio_task, "quec_gpio_test", 2, 0);
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