240 lines
13 KiB
C
240 lines
13 KiB
C
/*--------------------------------------------------------------------------------------------------------------------
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(C) Copyright 2006, 2007 Marvell DSPC Ltd. All Rights Reserved.
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-------------------------------------------------------------------------------------------------------------------*/
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/*********************************************************************
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* M O D U L E B O D Y *
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**********************************************************************
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* Title: Direct Memory Access - DMA *
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* *
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* Filename: dma_hw.h *
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* *
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* Target, platform: Arbel Platform, Tavor *
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* *
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* Author: Olga Fomenko *
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* *
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* Description: This is the HARDWARE file header for the DMA pacakge *
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* in contains all the hardware definitions for DMA and *
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* internal type definitions *
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* Notes: *
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**********************************************************************
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*/
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#ifndef _DMA_HW_H_
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#define _DMA_HW_H_
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#include "global_types.h"
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#define DMA_HW_BASE_ADDRESS 0xFFD01000
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//#define CDMA1_MUX_REGISTER 0xFFA04010 // used by MSA only
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#ifdef PHS_SW_DEMO_TTC
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#define CDMA2_MUX_REGISTER 0xF0240004
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#else
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#define CDMA2_MUX_REGISTER 0xF0204004
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#define CDMA3_MUX_REGISTER 0xF0204008
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#endif
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#define DMA_HW_CHANNELS_PER_CONTROLLER 8 // number of channels supported by each controller
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#ifdef PHS_SW_DEMO_TTC
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#define DMA_NUMBER_OF_DMA_HW_CONTROLLERS 2 // DMA C1 - 0xFFD01000, DMA C2 - 0xFFD02000
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#else
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#define DMA_NUMBER_OF_DMA_HW_CONTROLLERS 3 // DMA C1 - 0xFFD01000, DMA C2 - 0xFFD02000, & DMA C3 - 0xFFD03000
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#endif
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#define DMA_TOTAL_NUMBER_OF_CHANNELS (DMA_HW_CHANNELS_PER_CONTROLLER * DMA_NUMBER_OF_DMA_HW_CONTROLLERS)
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#define DMA_TIMEOUT_STOP_COUNT 5000 // number of times "wait loop" in stopChannel service run
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#define DMA_SIZE_OF_RESERVED_MEMORY_BLOCK 0xF70 // 0x2000-0x1090
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#define DMA_MAX_NUMBER_OF_PACKETS 1023
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typedef struct
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{
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UINT32 DCSAR; // DMA Channel Source Address Register R/W
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UINT32 DCDAR; // DMA Channel Destination Address Register R/W
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UINT32 DCBCR; // DMA Channel Byte Count Register R/W
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UINT32 DCCR; // DMA Channel Control Register R/W
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} DMA_ChannelHWRegistersS;
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typedef struct
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{
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UINT32 DCR; // DMA C1 Control Register R/W1
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UINT32 Reserved1; //
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UINT32 DESR; // DMA C1 Error Source Register R/W1
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UINT32 Reserved2;
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DMA_ChannelHWRegistersS ChannelRegister[DMA_HW_CHANNELS_PER_CONTROLLER];
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UINT8 Reserved[DMA_SIZE_OF_RESERVED_MEMORY_BLOCK];
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}DMA_ControllerRegistersS;
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typedef struct
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{
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//DMA_ControllerRegisters controller[DMA_NUMBER_OF_DMA_HW_CONTROLLERS];
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DMA_ControllerRegistersS controller[DMA_NUMBER_OF_DMA_HW_CONTROLLERS];
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}DMA_HardwareRegistersS;
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#define DmaHwRegisters (*(volatile DMA_HardwareRegistersS *)DMA_HW_BASE_ADDRESS)
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// DMAC MUX register
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#define DMA_MUX_REGISTER_CHANNEL_SHIFT(logicalChannel) (logicalChannel*2)
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#define DMA_MUX_REGISTER_CHANNEL_MASK(logicalChannel) (0x00000003 << DMA_MUX_REGISTER_CHANNEL_SHIFT(logicalChannel))
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//------------------ DMA Error Source Register masks ----------------------
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// setting this mask clear DESR register for all channel - initialization
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#define DMA_DESR_CLEAR_MASK 0xFFFF00FF
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// this mask purpose is clearing error bits of only one channel (by default-0).
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// to setting this mask to channel X => do shift rigth X of thos mask
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#define DMA_DESR_CHANNEL0_MASK 0x80800080
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//------------------ DMA Control Register ----------------------------------
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// setting this bit starts the channel
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// points to channel "0" start bit, do bitwise shift right for other channels
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#define DMA_CHANNEL_START_BIT 0x80000000
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// setting this bitterminates channel execution
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// points to channel "0" terminate bit, do bitwise shift right for other channels
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#define DMA_CHANNEL_TERMINATE_BIT 0x00800000
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//------------------ DMA Control Channel Register masks ---------------------
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// Go Enable bit: 1-go-enable mode transaction; 0-one-shot mode transaction
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#define DMA_CCR_GE_BIT_MASK 0x80000000
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// Interrupt Enable bit
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#define DMA_CCR_IE_BIT_MASK 0x20000000
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// Transfer size bits
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#define DMA_CCR_TSZ_MASK 0x00C00000
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#define DMA_CCR_TSZ_BYTE_MASK 0x00000000 // transfer in 8-bit units
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#define DMA_CCR_TSZ_WORD_MASK 0x00400000 // transfer in 16-bit units
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#define DMA_CCR_TSZ_DWORD_MASK 0x00800000 // transfer in 32-bit units
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#define DMA_CCR_TSZ_QWORD_MASK 0x00C00000 // transfer in 64-bit units
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// Source Addr Post modifier bits
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#define DMA_CCR_SAPM_MASK 0x00300000
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#define DMA_CCR_SAPM_SHIFT 20 // 00=>inc; 01=>dec; 10=>no change; 11=>reserved
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// Destination Addr Post modifier bits
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#define DMA_CCR_DAPM_MASK 0x000C0000 // 00=>inc; 01=>dec; 10=>no change; 11=>reserved
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#define DMA_CCR_DAPM_SHIFT 18
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// Transfer direction bit
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#define DMA_CCR_TD_BIT_MASK 0x00010000
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// #define DMA_A2B 0 // transfer from port A to port B
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// #define DMA_B2A 1 // transfer from port B to port A
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// Request to Channel Mapping
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#define DMA_CCR_RTCM_MASK 0x00007000 // 000-DMA_REQ[0]...111-DMA_REQ[7]
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#define DMA_CCR_RTCM_SHIFT 12
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// DMA Byte Count Register
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#define DMA_PLEN_MASK 0x3FFF0000 // Packet Length (set in the TSZ)
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#define DMA_PLEN_SHIFT 16
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#define DMA_PCNT_MASK 0x000003FF // Packet Count
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#define DMA_EWD_MASK 0x00008000
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#define DMA_EWOD_MASK 0x00004000
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/////////////////////////////////////////////////////////////////////
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// basic MACROS - In-Line functions
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/////////////////////////////////////////////////////////////////////
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#define DMA_CHANNEL_SET_GO_ENABLE(channel) ( (DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCCR) |= \
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DMA_CCR_GE_BIT_MASK )
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#define DMA_CHANNEL_CLEAR_GO_ENABLE(channel) ( (DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCCR) &= \
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(~DMA_CCR_GE_BIT_MASK) )
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#define DMA_CHANNEL_SET_INTERRUPT_ENABLE(channel) ( (DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCCR) |= \
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DMA_CCR_IE_BIT_MASK )
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#define DMA_CHANNEL_CLEAR_INTERRUPT_ENABLE(channel) ( (DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCCR) &= \
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(~DMA_CCR_IE_BIT_MASK) )
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#define DMA_CLEAR_DCCR(channel) { DMA_CHANNEL_SET_GO_ENABLE(channel); \
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DMA_CHANNEL_SET_INTERRUPT_ENABLE(channel);}
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#define DMA_GET_CONTROLLER_NUMBER(channel) (channel>>3) // channle/DMA_HW_CHANNELS_PER_CONTROLLER)
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#define DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel) (channel & 0x07L) //(channel%DMA_HW_CHANNELS_PER_CONTROLLER )
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#define DMA_CLEAR_DESR(channel) { DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].DESR |= \
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DMA_DESR_CLEAR_MASK ;}
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#define DMA_SET_SOURCE_ADDR(channel, addr) {DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCSAR = \
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(UINT32)addr;}
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#define DMA_SET_DEST_ADDR(channel, addr) {DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCDAR = \
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(UINT32)addr;}
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#define DMA_CLEAR_DESR_CHANNEL_BITS(channel) {DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].DESR |= \
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( DMA_DESR_CHANNEL0_MASK >> DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel) );}
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#define DMA_SET_DIRECTION_A2B(channel) {DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCCR &= \
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(~DMA_CCR_TD_BIT_MASK);}
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#define DMA_SET_DIRECTION_B2A(channel) {DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCCR \
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|= DMA_CCR_TD_BIT_MASK;}
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#define DMA_SET_PACKET_LEN(channel, packetLength) { DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCBCR &= (~DMA_PLEN_MASK);\
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DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCBCR |= \
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(packetLength <<16);}
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#define DMA_SET_PACKET_COUNT(channel, packetCount) { DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCBCR &= (~DMA_PCNT_MASK);\
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DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].ChannelRegister[DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)].DCBCR |= packetCount;}
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#define DMA_IS_CHANNEL_ERROR(channel) ( DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].DESR & \
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(DMA_DESR_CHANNEL0_MASK>>DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel) ))
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//TBD
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#define DMA_IS_CHANNEL_ENDED(channel) (TRUE)
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#ifdef DMA_DEBUG
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#define DEBUG_GPO0_SET (*(UINT32 *)0xD4060208 = 0x1)
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#define DEBUG_GPO0_CLEAR (*(UINT32 *)0xD406020C = 0x1)
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#define DEBUG_GPO1_SET (*(UINT32 *)0xD4060208 = 0x2)
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#define DEBUG_GPO1_CLEAR (*(UINT32 *)0xD406020C = 0x2)
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#endif //DMA_DEBUG
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// these registers exist only in A0
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#define DMAC_EOCINH_WR_BASE 0xF0260000
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//#define DMAC1_EOCINH_WR_OFFSET 0x0
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//#define DMAC2_EOCINH_WR_OFFSET 0x4
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//#define DMAC3_EOCINH_WR_OFFSET 0x8
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#define DMAC_EOCINH_EOIC_BIT_MASK 0x1
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#ifdef PHS_SW_DEMO_TTC
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#define DMA_ENABLE_EOC(controller, channel) ( (controller==0)?(*(UINT32*)0xFFB00018):(*(UINT32*)0xF0240008)) = ((channel<<1)|DMAC_EOCINH_EOIC_BIT_MASK) )
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#else
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#define DMA_ENABLE_EOC(controller, channel) ( *(UINT32*)(DMAC_EOCINH_WR_BASE+4*(controller)) = ((channel<<1)|DMAC_EOCINH_EOIC_BIT_MASK) )
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#endif
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#if 0
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#ifdef PHS_SW_DEMO_TTC
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#define DMA_ENABLE_EOC(controller, channel) ( (controller==0)?(*(UINT32*)0xFFB00018):(*(UINT32*)0xF0240008)) = ((channel<<1)|DMAC_EOCINH_EOIC_BIT_MASK) )
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#else
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#define DMA_DISABLE_EOC(controller, channel) ( *(UINT32*)(DMAC_EOCINH_WR_BASE+4*(controller)) = (channel<<1) )
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#endif
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#else
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#ifdef PHS_SW_DEMO_TTC
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//#define DMA_DISABLE_EOC(controller, channel) ( (controller==0)?(*(UINT32*)0xFFB00018):(*(UINT32*)0xF0240008)) = (channel<<1)
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#define DMA_DISABLE_EOC(controller, channel) \
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if(controller==0) \
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*(UINT32*)0xFFB00018 = (channel<<1); \
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else \
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*(UINT32*)0xF0240008 = (channel<<1);
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#else
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#define DMA_DISABLE_EOC(controller, channel) ( *(UINT32*)(DMAC_EOCINH_WR_BASE+4*(controller)) = (channel<<1) )
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#endif
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#endif
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#endif // _DMA_HW_H_
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