269 lines
8.8 KiB
C
269 lines
8.8 KiB
C
#ifndef _SPI_NOR_H_
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#define _SPI_NOR_H_
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#define BIT(n) (1<<(n))
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#define SSP_READ_TIME_OUT_MILLI 0x200
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#define SSP_READ_DMA_DESC 0x10 //total RX descriptors
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#ifdef SPI_MUX
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#define SSP_READ_DMA_SIZE 0x100 //bytes per descriptor
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#else
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#define SSP_READ_DMA_SIZE 0x1000 //bytes per descriptor
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#endif
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#define WRITE_SIZE (256)
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#define SZ_4K 0x00001000
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#define SZ_32K 0x00008000
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#define SZ_64K 0x00010000
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#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
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#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (up to 256 bytes) */
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#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block (up to 256 bytes) */
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#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block (up to 256 bytes)*/
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#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB, up to 256 bytes) */
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#define MAX_CMD_SIZE 6
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#define BIT_0 (1 << 0)
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#define BIT_1 (1 << 1)
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#define BIT_2 (1 << 2)
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#define BIT_3 (1 << 3)
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#define BIT_4 (1 << 4)
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#define BIT_5 (1 << 5)
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#define BIT_6 (1 << 6)
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#define BIT_7 (1 << 7)
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#define BIT_8 (1 << 8)
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#define BIT_9 (1 << 9)
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#define BIT_10 (1 << 10)
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#define BIT_11 (1 << 11)
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#define BIT_12 (1 << 12)
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#define BIT_13 (1 << 13)
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#define BIT_14 (1 << 14)
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#define BIT_15 (1 << 15)
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#define BIT_16 (1 << 16)
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#define BIT_17 (1 << 17)
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#define BIT_18 (1 << 18)
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#define BIT_19 (1 << 19)
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#define BIT_20 (1 << 20)
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#define BIT_21 (1 << 21)
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#define BIT_22 (1 << 22)
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#define BIT_23 (1 << 23)
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#define BIT_24 (1 << 24)
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#define BIT_25 (1 << 25)
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#define BIT_26 (1 << 26)
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#define BIT_27 (1 << 27)
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#define BIT_28 (1 << 28)
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#define BIT_29 (1 << 29)
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#define BIT_30 (1 << 30)
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#define BIT_31 ((unsigned)1 << 31)
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typedef unsigned long long uint64_t;
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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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typedef unsigned int uint32_t;
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#define ADDR_ALIGN(addr_, align_) ((addr_+align_-1)&(~(align_-1)))
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
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struct DMA_CMD_BITS
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{
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uint32_t Length :13; //Bits [12:0]: Length of transfer in Bytes
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uint32_t Reserved4 :1; //Bit 13: reserved
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uint32_t Width :2; //Bits [15:14]: Width of onchip peripheral - 0=reserved, 1=1B, 2=2B, 3=4B
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uint32_t MaxBurstSize :2; //Bits [17:16]: Max Burst Size - 0=reserved, 1=8B, 2=16B, 3=32B
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uint32_t Reserved3 :3; //Bits [20:18]: reserved
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uint32_t EndIRQEn :1; //Bit 21: end interrupt enable
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uint32_t StartIRQEn :1; //Bit 22: start interrupt enable
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uint32_t AddrMode :1; //Bit 23: Addressing mode for descriptor compare - 0=target has addr/1=target has data
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uint32_t Reserved2 :1; //Bit 24: reserved
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uint32_t CmpEn :1; //Bit 25: Compare Enable - descriptor branching compare enable
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uint32_t Reserved1 :2; //Bits [27:26]: reserved
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uint32_t FlowTrg :1; //Bit 28: Target flow control - 1=wait for request signal
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uint32_t FlowSrc :1; //Bit 29: Source flow control - 1=wait for request signal
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uint32_t IncTrgAddr :1; //Bit 30: Target increment - 0=no increment, 1=increment
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uint32_t IncSrcAddr :1; //Bit 31: Source increment - 0=no increment, 1=increment
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};
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typedef struct DMA_DESCRIPTOR_TAG{
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uint32_t DDADR; // descriptor address reg
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uint32_t DSADR; // source address register
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uint32_t DTADR; // target address register
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uint32_t DCMD; // command address register
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}DMA_DESCRIPTOR, *P_DMA_DESCRIPTOR;
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typedef union
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{
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uint32_t value;
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struct DMA_CMD_BITS bits;
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} DMA_CMDx_T, *P_DMA_CMDx_T;
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#ifndef SPINOR_MAX_ID_LEN
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#define SPINOR_MAX_ID_LEN 4
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#endif
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#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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.id = { \
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((_jedec_id) >> 24) & 0xff, \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.id_len = 4, \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = 256, \
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.flags = (_flags),
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#define SPI_NOR_CMD(_jedec_id, _enable_4byte, _disable_4byte, _read_status, _write_status, \
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_sector_erase_4k, _blk_erase_32k, _blk_erase_64k, _chip_erase, _prog, _wr_enable, \
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_wr_disable, _read_id, _en_rst, _reset, _release_powerdown, _cache_read, _max_cmd) \
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.id = { \
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((_jedec_id) >> 24) & 0xff, \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.enable_4byte = (_enable_4byte), \
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.disable_4byte = (_disable_4byte), \
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.read_status = (_read_status), \
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.write_status = (_write_status), \
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.sector_erase_4k = (_sector_erase_4k), \
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.blk_erase_32k = (_blk_erase_32k), \
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.blk_erase_64k = (_blk_erase_64k), \
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.chip_erase = (_chip_erase), \
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.prog = (_prog), \
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.wr_enable = (_wr_enable), \
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.wr_disable = (_wr_disable), \
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.read_id = (_read_id), \
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.en_rst = (_en_rst), \
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.reset = (_reset), \
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.release_powerdown = (_release_powerdown), \
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.cache_read = (_cache_read), \
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.max_cmd = (_max_cmd),
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struct nor_info {
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char *name;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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uint8_t id[SPINOR_MAX_ID_LEN];
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uint8_t id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned sector_size;
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uint16_t n_sectors;
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uint16_t page_size;
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uint16_t addr_width;
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uint16_t flags;
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#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
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#define SST_WRITE BIT(2) /* use SST byte programming */
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#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
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#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
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#define USE_FSR BIT(7) /* use flag status register */
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#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
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#define SPI_NOR_HAS_TB BIT(9) /*
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* Flash SR has Top/Bottom (TB) protect
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* bit. Must be used with
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* SPI_NOR_HAS_LOCK.
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*/
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#define SPI_NOR_4B_OPCODES BIT(11) /*
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* Use dedicated 4byte address op codes
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* to support memory size above 128Mib.
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*/
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};
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struct spinor_chip_info;
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struct spinor_ops {
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int (*reset)(struct spinor_chip_info *chip);
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int (*read_id)(struct spinor_chip_info *chip, uint8_t *buf);
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#ifdef QUEC_NVM_IN_EXT_FLASH
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int (*read)(struct spinor_chip_info *chip, uint32_t addr, int Size, uint32_t Buffer);
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#else
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int (*read)(struct spinor_chip_info *chip, uint32_t FlashOffset, int Size, uint32_t Buffer);
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#endif
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int (*write)(struct spinor_chip_info *chip, uint32_t addr, int Size, uint32_t Buffer);
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#ifdef QUEC_NVM_IN_EXT_FLASH
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int (*erase)(struct spinor_chip_info *chip, int offset, int size);
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#else
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int (*erase)(struct spinor_chip_info *chip);
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#endif
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int (*erase_sector)(struct spinor_chip_info *chip, int offset, int size);
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};
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struct spinor_cmd_cfg {
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char *name;
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uint8_t id[SPINOR_MAX_ID_LEN];
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uint8_t enable_4byte;
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uint8_t disable_4byte;
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uint8_t read_status;
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uint8_t write_status;
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uint8_t sector_erase_4k;
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uint8_t blk_erase_32k;
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uint8_t blk_erase_64k;
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uint8_t chip_erase;
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uint8_t prog;
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uint8_t wr_enable;
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uint8_t wr_disable;
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uint8_t read_id;
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uint8_t en_rst;
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uint8_t reset;
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uint8_t release_powerdown;
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uint8_t cache_read;
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uint8_t max_cmd;
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};
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typedef enum
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{
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DMA_STOP = 0,
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DMA_END
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}DMA_WAIT_DONE_FLAG;
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struct spinor_chip_info {
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struct nor_info *info;
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struct spinor_cmd_cfg *table;
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struct spinor_ops *ops;
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uint8_t addr_width;
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};
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#if 0
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struct test_config
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{
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uint32_t pattern;
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int len;
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};
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#endif
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struct spinor_cmd {
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uint8_t n_addr; /* Number of address */
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//uint32_t cmdtmp;
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const uint8_t *cmdtmp;
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uint32_t n_tx; /* Number of tx bytes */
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const uint8_t *tx_buf; /* Tx buf */
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uint32_t n_rx; /* Number of rx bytes */
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uint8_t *rx_buf; /* Rx buf */
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uint8_t mode;
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uint32_t command;
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};
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//int spinor_test(uint8_t argc, uint8_t **argv);
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struct spinor_chip_info *spinor_init(const char *name, int clk);
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#endif
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