140 lines
3.8 KiB
C
140 lines
3.8 KiB
C
#ifndef _QSPI_H_
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#define _QSPI_H_
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#include <stdlib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* QSPI register address offset definitions
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*/
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#define QSPI_MCR 0x000
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#define QSPI_TCR 0x004
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#define QSPI_IPCR 0x008
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#define QSPI_FLSHCR 0x00C
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#define QSPI_BUF0CR 0x010
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#define QSPI_BUF1CR 0x014
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#define QSPI_BUF2CR 0x018
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#define QSPI_BUF3CR 0x01C
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#define QSPI_BFGENCR 0x020
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#define QSPI_SOCCR 0x024
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#define QSPI_BUF0IND 0x030
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#define QSPI_BUF1IND 0x034
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#define QSPI_BUF2IND 0x038
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#define QSPI_SFAR 0x100
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#define QSPI_SFACR 0x104
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#define QSPI_SMPR 0x108
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#define QSPI_RBSR 0x10C
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#define QSPI_RBCT 0x110
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#define QSPI_TBSR 0x150
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#define QSPI_TBDR 0x154
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#define QSPI_TBCT 0x158
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#define QSPI_SR 0x15C
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#define QSPI_FR 0x160
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#define QSPI_RSER 0x164
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#define QSPI_SPNDST 0x168
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#define QSPI_SPTRCLR 0x16C
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#define QSPI_SFA1AD 0x180
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#define QSPI_SFA2AD 0x184
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#define QSPI_SFB1AD 0x188
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#define QSPI_SFB2AD 0x18C
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#define QSPI_DLPR 0x190
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#define QSPI_RBDR0 0x200
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#define QSPI_LUTKEY 0x300
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#define QSPI_LCKCR 0x304
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#define QSPI_LUT0 0x310
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/*
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* QSPI clock freqency definitions
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*/
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#define QSPI_CLOCK_13MHZ 1
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#define QSPI_CLOCK_26MHZ 3
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#define QSPI_CLOCK_39MHZ 4
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#define QSPI_CLOCK_52MHZ 5
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#define QSPI_CLOCK_78MHZ 6
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#define QSPI_CLOCK_104MHZ 7
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/*
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* QSPI LUT instrcutions
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*/
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#define QSPI_INST_STOP 0x0
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#define QSPI_INST_CMD 0x1
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#define QSPI_INST_ADDR 0x2
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#define QSPI_INST_DUMMY 0x3
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#define QSPI_INST_MODE 0x4
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#define QSPI_INST_MODE2 0x5
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#define QSPI_INST_MODE4 0x6
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#define QSPI_INST_READ 0x7
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#define QSPI_INST_WRITE 0x8
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#define QSPI_INST_JMP_ON_CS 0x9
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#define QSPI_INST_ADDR_DDR 0xA
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#define QSPI_INST_MODE_DDR 0xB
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#define QSPI_INST_MODE2_DDR 0xC
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#define QSPI_INST_MODE4_DDR 0xD
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#define QSPI_INST_READ_DDR 0xE
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#define QSPI_INST_WRITE_DDR 0xF
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#define QSPI_INST_DATA_LEARN 0x10
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/*
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* QSPI LUT pads
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*/
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#define QSPI_PAD_1X 0x0
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#define QSPI_PAD_2X 0x1
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#define QSPI_PAD_4X 0x2
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/*
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* QSPI TX/RX fifo size
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*/
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#define QSPI_TX_FIFO_SIZE 128
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#define QSPI_RX_FIFO_SIZE 128
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/*
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* QSPI flash device address offset
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*/
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#define QSPI_FLASH_A1_OFFSET 0x00000000
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#define QSPI_FLASH_A2_OFFSET 0x08000000
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#define QSPI_FLASH_B1_OFFSET 0x10000000
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#define QSPI_FLASH_B2_OFFSET 0x18000000
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/*
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* QSPI TX FIFO watermark
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*/
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#define QSPI_TX_FIFO_WATERMARK_4_BYTE 0
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#define QSPI_TX_FIFO_WATERMARK_8_BYTE 1
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#define QSPI_TX_FIFO_WATERMARK_32_BYTE 7
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#define QSPI_TX_FIFO_WATERMARK_64_BYTE 15
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#define RSER_TBTDE (1 << 25) /* TX Buffer Fill DMA Enable */
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typedef struct {
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unsigned addr; /* offset address */
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unsigned value; /* register value */
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} qspi_register_config_t;
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typedef union {
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struct {
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unsigned oprndi0 : 8; /* operand for instr0 */
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unsigned pad0 : 2; /* pad information for instr0 */
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unsigned instr0 : 6; /* instruction 0 */
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unsigned oprndi1 : 8; /* operand for instr1 */
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unsigned pad1 : 2; /* pad information for instr1 */
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unsigned instr1 : 6; /* instruction 1 */
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} s;
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unsigned value;
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} qspi_lut_config_t;
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int qspi_init(int clock_freq, unsigned offset_addr);
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void qspi_register_config(const qspi_register_config_t *config);
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int qspi_lut_config(const qspi_lut_config_t *config, unsigned index);
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void qspi_cmd(unsigned seqid, unsigned addr);
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int qspi_read(unsigned seqid, unsigned addr, void *data, size_t size);
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int qspi_write(unsigned seqid, unsigned addr, const void *data, size_t size);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _QSPI_H_ */
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