77 lines
2.0 KiB
C
77 lines
2.0 KiB
C
#ifndef __NGPIO_HW_H__
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#define __NGPIO_HW_H__
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#define GPIO_MAX_PORT_HANDLERS 128
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#define APB_AP_CLOCK_CTRL_BASE 0xD4015000
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#define APBC_GPIO_CLC_RST (APB_AP_CLOCK_CTRL_BASE+0x8)
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#define GPIO_REGISTER_BASE 0xD4019000
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#define GPIO_REGISTER_GROUPS 4
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#define GPIO_GROUP_BASE1 0
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#define GPIO_GROUP_BASE2 4
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#define GPIO_GROUP_BASE3 8
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#define GPIO_GROUP_BASE4 0x100
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#define GPIO_EDGE_BASE 0xD4019800
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//mfpr edge reg address = base + int(gpio/32)*4
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#define MFPR_EDGE_ADDR(n) (GPIO_EDGE_BASE + ((n >> 5) << 2));
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#define GPIO_SHIFT(gpio) (1 << (gpio%32))
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/*bit definition for GPIO functions*/
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#define GPIO_BIT_ENABLE_RED (1 << 4)
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#define GPIO_BIT_ENABLE_FED (1 << 5)
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#define GPIO_BIT_CLEAR_ED (1 << 6)
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#define GPIO_BIT_SLEEP_DIR (1 << 7)
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#define GPIO_BIT_DRIVE_0 (1 << 11)
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#define GPIO_BIT_DRIVE_1 (1 << 12)
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#define GPIO_BIT_PULLDN (1 << 13)
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#define GPIO_BIT_PULLUP (1 << 14)
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#define GPIO_BIT_PULL_SEL (1 << 15)
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typedef struct
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{
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UINT32 REG;
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UINT32 padding[2];
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}GPIO_Single_Register;
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typedef volatile struct
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{
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volatile GPIO_Single_Register PLR;//0x0
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volatile GPIO_Single_Register PDR;//0xc
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volatile GPIO_Single_Register PSR;//0X18
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volatile GPIO_Single_Register PCR;//0X24
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volatile GPIO_Single_Register RER;//0X30
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volatile GPIO_Single_Register FER;//0X3C
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volatile GPIO_Single_Register EDR;//0X48
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volatile GPIO_Single_Register SDR;//0X54
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volatile GPIO_Single_Register CDR;//0X60
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volatile GPIO_Single_Register SRER;//0X6C
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volatile GPIO_Single_Register CRER;//0X78
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volatile GPIO_Single_Register SFER;//0X84
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volatile GPIO_Single_Register CFER;//0X90
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volatile GPIO_Single_Register AP_MASK;//0X9C
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volatile GPIO_Single_Register CP_MASK;//0XA8
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}GPIORegisters;
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typedef enum
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{
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VSPI_GPIO_0=0,
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VSPI_GPIO_32=32,
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VSPI_GPIO_33=33,
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VSPI_GPIO_34,
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VSPI_GPIO_35,
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VSPI_GPIO_36,
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VSPI_GPIO_64=64,
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VSPI_GPIO_96=96,
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VSPI_GPIO_121=121,
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VSPI_GPIO_MAX=127,
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VSPI_GPIO_NULL=128
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}VSpiGpio;
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#endif
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